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AXI interface in Qsys 11.1

Altera_Forum
Honored Contributor II
1,454 Views

Hello. 

 

I have a question regarding the use of AXI interconnect in Qsys 11.1. 

 

I have the VHDL component, which must communicate with NIOS processor through AXI interface. 

 

First of all, I don't see that NIOS processor has AXI interface at all. 

 

Yet, I see that in Components library of Qsys under Qsys Interconnect there's "AXI Interface" section with 2 components : AXI Master Network Interface and AXI Slave Network Interface. 

 

AXI Slave Network Interface accepts command packets on avalon_streaming interface and issues the resulting transactions to the AXI interface. 

 

Question: 

 

1) Does it mean that for connecting my IP to NIOS I should first translate Avalon-MM interface of NIOS to Avalon-ST interface, and after that use AXI Slave Network Interface? 

 

2) There's no any documentation on AXI Master and Slave blocks. There're a lot of parameters inside which must be set somehow. Can anyone explain what do they mean? 

 

Thanks in advance. 

 

Best regards, 

 

Dima.
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5 Replies
Altera_Forum
Honored Contributor II
141 Views

1) Yes you'll be able to mix systems that use components with Avalon-MM and AXI interfaces. 

 

2) It's beta so that's why the information is limited: http://www.alterawiki.com/wiki/axi_support 

 

 

Altera_Forum
Honored Contributor II
141 Views

BadOmen, thank you for a quick reply. 

 

The mix of Avalon-MM and AXI interfaces that you mentioned seems to be not so simple. Especially due to the lack of documentation. 

 

Currently I don't have any idea how to connect NIOS processor to my AXI peripheral.
Altera_Forum
Honored Contributor II
141 Views

It's beta so that normally means no documentation. My advice is unless you have an Altera FAE that is familar with the AXI support I would wait until it is formally released. If you created a peripheral that supports a limited subset of what is available in AXI I think it should be possible to have Avalon transactions reach the AXI side. The goal is to have AXI and Avalon based IP be able to move data back and forth but whether you can do that today even with simple transactions I'm not 100% sure myself (haven't attempted this).

Altera_Forum
Honored Contributor II
141 Views

 

--- Quote Start ---  

It's beta so that normally means no documentation. My advice is unless you have an Altera FAE that is familar with the AXI support I would wait until it is formally released. If you created a peripheral that supports a limited subset of what is available in AXI I think it should be possible to have Avalon transactions reach the AXI side. The goal is to have AXI and Avalon based IP be able to move data back and forth but whether you can do that today even with simple transactions I'm not 100% sure myself (haven't attempted this). 

--- Quote End ---  

 

 

BadOmen: 

Now that Altera has released 12.1 with SP1, does Qsys support complete AXI4 protocol? I have connected an AXI4 component to Qsys interconnect. I was able to do register accesses with out any issues, but burst transfers seem to have a problem.  

 

Regards 

Bhargav
Altera_Forum
Honored Contributor II
141 Views

Page 41 of this document states that bursting should work: http://www.altera.com/literature/hb/qts/qsys_interconnect.pdf

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