Hey guys,I've made a custom component to interface between Nios and some verilog. I've attached a screenshot of the signals. If a FIFO megafunction from 9.1 (because FIFO makes 10.1 and 11 crash). how do i access these avalon signals within nios c code? I've googled the sh+t out of it and come up with nothing. I've skimmed the Avalon manuals but can't see what i do. Watching the Avalon training course and it doesn't show how. It can't be a direct address access since the components address is only 3 bits (base and end). As seen in the picture there are 3 slave connections with one of them being 32bit. Any advice would be awesome, Thanks in Advance
--- Quote Start --- how do i access these avalon signals within nios c code? --- Quote End --- You don't access the signals. You access the address at which the device will respond to read/write accesses. A FIFO will map to a single address. What you really need to do when developing a custom component is to create an SOPC system with an Avalon-MM BFM master and use that to generate read/write transactions to your device-under-test. To integrate a FIFO into an SOPC System, to start with you should create a Avalon-MM write-only slave (for writing to the FIFO), and an Avalon-MM read-only slave (for reading from the FIFO). It does not matter if this is what your design requires, as at some point, you may need either component. If you have never used the Verification-IP suite, there are online webinars that explain it quite well. Cheers, Dave
Nios II only can access memory mapped slave *interfaces* not the signals that make up the interface. To access this FIFO you probably should include "io.h" and use one of the IORD macros defined in it. Searching for "io.h" or "IORD" in the Nios II software handbook for more details. These macros perform cache bypassing read accesses to whatever address you pass into it.