Add other file (vhdl) in project with .qip.

[Altera_Forum]

Hi, good morning,  

  I'm trying add another file (vhdl) in quartus project, with .qip. I need that my application has an little module in vhdl, but I'm not getting run. Or may set an file as top level or another file, this problem prevents the allocation of pins, since only the pins of top level are avaiable for allocation.  Can anyone help me ?  Thanks.

[Altera_Forum]

Not sure what the question is - you can only assign pins to the top level module. If you need to add a sub module that connects to pins on the device, you need to route the signals up to the top level.

[Altera_Forum]

Hi, Tricky,  

 Do you know how can i route the signals up to the top level ?  Thanks.

[Altera_Forum]

You need to modify the source files.

[Altera_Forum]

Ok, but this process i do directly in quartus or qsys ?

[Altera_Forum]

Just to understand your setup, I think you have a Qsys system, which you have generated, with some ports, ie clock and reset exported (within Qsys) and you have another VHDL file that you would like to connect it to the Qsys system and extra pins that you would want to assign to some pins? 

 If the above statement is true, you will need to create a top level RTL (or another VHDL file) to instantiate both the Qsys system and your own VHDL file and connect them. You will need to set the top level RTL as the top level entity. It should also contain all the pins that needed to be assigned at the pin planner.