Address missmatch in triple_speed_ethernet tutorial when setting Block Diagram as Top

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Address missmatch in triple_speed_ethernet tutorial when setting Block Diagram as Top

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Hallo,

i have a Verilog file from the tutorial: "Using Triple Speed Ethernet on DE2-115 Boards"

ftp://ftp.altera.com/up/pub/altera_material/12.0/tutorials/de2-115/using_triple_speed_ethernet.pdf

I am trying to build the same verilog file in a Block diagramm and set it as a Top Entity.

In the verilog file, i have 3 Instances. I took the Instances and added them seperatly to the Block Diagramm.

My project ist working fine with the Verilog file as Top entity.

When i set the Block diagramm as Top Entity, i get some problems in Eclipse:

Verifying 00080000 ( 0%)

Verify failed between address 0x80000 and 0x86183

Leaving target processor paused

I compared the designs in RTL viewer. Both designs in RTL Viewer look alike !

Anyone have a clue whats going wrong ?

I need to seperate the 3 Inst. in the Block Diagramm and i cant use the option "create Symvol Files for current file" !!

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