- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi everyone,
I have sucessfully integrated the Altera Avalon MM Read Master template. However, this only works properly up to the length of 20. (word size is 32 bit) When I define the transfer length to be 24, i.e. 6 words, then there are only 5 dataavailable assertions with 5 buffered data. What I find interesting is, that the signal early_done does get asserted, meaning the last read is actually posted, but the signal done is never asserted, so somehow the result cannot be returned. I already used a FIFO of size 64, so should be big enough I think. Is this a known issue? Or anyone an idea what the problem could be? Best regards, JimmyLink Copied
1 Reply
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi, it will be faster to write Avalon MM Read Master by yourself than try debugging these templates. There are 3 parts here: send read addresses, react on waitrequest and collect incoming data on the bus.
Reply
Topic Options
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page