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Honored Contributor I

Altera Cyclone V PCIe Development Board Write Memory to Root Complex

Hello Altera-Forum, 


This post is about processing receiving unrequested data from an Altera Cyclone V development board IP core. The root complex is an Intel Haswell-CPU/SOC. The development board is plugged in the PCIe x16 slot. 

The PCIe specification is allowing the development board may to act as a master in the bus and send a write request TLP (Transaction Layer Packet). 


Is there a coding example existing for Linux to do this? Where will be the data written to, when the TLP has address 0x0 defined? 

The used OS is allowing to allocate a DMA memory map. Where in the allocated memory may appear the incoming data? 

Should I ask all this in the Intel developer forums? 


with my regards 


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