Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Altera_Forum
Honored Contributor I
1,494 Views

Altera SPI Slave to Avalon Master Bridge design example help/questions

Is anyone here familiar with the Altera SPI Slave to Avalon Master Bridge design Example? I am stuck on understanding/seeing some key details in its design/implementation. I am implementing this on a DE10 Lite FPGA Demo Board. This demo makes use of user flash. This demo makes use of two qsys components. The first qsys component sets up a NIOS II processor and runs a simple c program. The c program uses a c library to package up a transaction and send it over the spi bus to the second component. The code used to package a message to the second qsys component is portable. I will port it to a raspberri pi. The master/nios ii app simply sends commands to read and write memory connected to the fpga. 

 

 

The second qsys component receives these spi messages and returns/write connected on chip ram, which resides in flash memory. The design example places both of these components in the same pof file. The pof is downloaded and seems to work fine. 

 

 

 

 

Ultimately, I wish to remove one of the components, the master and place it on a raspberri pi and use the spi lines to send/receive messages. 

 

 

In the verlig example file, these two componets are internally wired as follows ... 

 

 

 

 

 

 

 

 

nios_spi_master nios_spi_master ( 

.clk_clk (IN_CLOCK), 

.reset_reset_n (IN_RESET_N), 

.led_export (led[7:4]), 

.spi_MISO (MISO), 

.spi_MOSI (MOSI), 

.spi_SCLK (SCLK), 

.spi_SS_n (SS_N) 

); 

 

 

spi_slave spi_slave ( 

.clk_clk (IN_CLOCK), 

.reset_reset_n (IN_RESET_N), 

.spi_mosi_to_the_spislave_inst_for_spichain (MOSI), 

.spi_nss_to_the_spislave_inst_for_spichain (SS_N), 

.spi_miso_to_and_from_the_spislave_inst_for_spichain (MISO), 

.spi_sclk_to_the_spislave_inst_for_spichain (SCLK), 

.switch_export (IN_SWITCH), 

.led_export (led[3:0]) 

); 

 

 

 

 

 

 

First question, is all the connection betwen these two qsys components happening on the common lines. MISO, SCLK, SS_N for examples? If it is, I shouldn't have any problem replicating the program between fpga and raspberri pi if the spi messages are the same? 

 

 

 

 

Second question, when I take a signal like SCLK and send it out to an FPGA pin, i see no indication of life? I initially thought it was because the clock was so fast, so i scaled the IN_CLOCK down to be only 5M, a fraction of the origional speed, which worked. I still see no indication of life on these spi lines. The spi message from master to slave would encapsulate a protocol to access an address of memory and return some data. The spi slave takes this message and gets it in its implementation. 

 

 

My main issue is that I cannot see the signals going back and fourth between the components in an oscilliscope. This example takes a sof file from the build. Takes a hex file from eclipse for the nios ii processor and using the convert programming file, stuffs it all into a single pof file. I then load the pof file to my board. 

 

 

 

 

Third question, Should the pof file be loaded to CFM0 or UFM? Does it make a difference? 

 

 

4TH Question: I am having issues using signal tapp logic analizer in this scenario. Should this tool work if I load into flash memory as described in the design example? 

 

 

Last question... Once loaded, if I switch to eclipse and right click on the project, for the c program build. I then click on the option tha says to run as nios ii hardware. afetr some messages pass through the screen, there is output from the c program, where is this output coming from? Is is simulated or is it actuall runnign/resetting a new instance on the fpga. when this option is selected, i see activity dorected towards the fpga and it seems like it is actually restarting the program to generate new output messages for viuewing in the terminal. 

 

 

 

 

 

 

My main issue here is that I cannot see the spi communication between the master and slave components. Other concerns of mine relate to using flash memory as the example uses for the spi slave and whit this does with regard to signal tap logic analizer? 

 

 

Thanks, Jeff
0 Kudos
2 Replies
Altera_Forum
Honored Contributor I
125 Views

I have an update to this... 

 

I did get the problem above ironed out. Another one, more of a setup question, developed after, and while I did not exactly solve that, I have a workaround. Long story short...I have a new problem that I need some insight into... 

 

I now have a raspberri pi that uses a library to send some bytes over spi wire to my fpga. The fpga receives these signals and sends them into the qsys component below. The below component would normally talk back on the miso line to the master, in this case, my raspberri pi. The pi would would properly continue on. My problem is that the spi slave doesn't acknolwedge teh communication when it should. 

 

 

The slave is below. 

 

spi_slave spi_slave ( 

.clk_clk (IN_CLOCK), 

.reset_reset_n (IN_RESET_N), 

.spi_mosi_to_the_spislave_inst_for_spichain (MOSI), 

.spi_nss_to_the_spislave_inst_for_spichain (SS_N), 

.spi_miso_to_and_from_the_spislave_inst_for_spicha in (MISO), 

.spi_sclk_to_the_spislave_inst_for_spichain (SCLK), 

.switch_export (IN_SWITCH), 

.led_export (led[3:0]) 

); 

 

 

When this slave is wired to a master inside the fpga, on the same clock, the communication works smoothly betwen master and slave. I saw the signals decoded on my oscilliscope and see exactly what is sent/received by the two parties. I also looked at this in signal tapp and nios debugger. When the master was a nios program on the fpga. 

 

When I take the library out of the nios code and put it in my rasdpberri pi and replicate the same transaction betwen the master and slave, the slave appears to be uninterested in replying back to the master when it should. Signal tapp shows the signals going into the fpga slave and my oscilliscope shows them to be the same. Any idea what the issue coul be? Both these components have differeny clocks but I'm not sure if that should mater?
Altera_Forum
Honored Contributor I
125 Views

You can probably delete this whole thread. I solved yesterdays problem. It had to do with the polarity of the SPI transaction.

Reply