Hi.I am trying to get Helio Cyclonse V SoC board working Baremetal environment. And I am trying it by using Altera-SoCFPGA-HardwareLib-GPIO-CV-GNU for DS-5. A problem I am having now is on boot process/preloader, I get a message saying "CALIBRATION FAILED" I've tried on two boards but the results are the same. Altera-SoCFPGA-HardwareLib-GPIO-CV-GNU is the one of SoC Design Example available from Altera web page and I believe it is the latest so far. DS-5 version is 15.1 and it is not the evaluation version. My Board is Rev 1.4 Please give me your advises. Thank you. Below is the message from UART. U-Boot SPL 2013.01.01 (Oct 22 2015 - 16:13:29) BOARD : Altera SOCFPGA Cyclone V board CLOCK: EOSC1 clock 25000 KHz CLOCK: EOSC2 clock 25000 KHz CLOCK: F2S_SDR_REF clock 0KHz CLOCK: F2S_PER_REF clock 0KHz CLOCK: MPU clock 925 MHz CLOCK: DDR clock 400MHz CLOCK: UART clock 100000 KHz CLOCK: MMU clock 50000 KHz CLOCK: QSPI clock 370000 KHz RESET: COLD SDRAM: Initializing MMR registers SDRAM: Calibration PHY SEQ.C: Preparing to start memory calibration SEQ.C: CALIBRATION FAILED# ## ERROR# ## Please RESET the board# ##
Hi.Thanks for your advise. The error is actually happening from, CAL STAGE VFIFO (Stage 1) and CAL_SUBSTAGE_GUARANTEED_READ (Substage 1). The error group is 4. I am still not sure why it is happening. Is there anything I can do for it? :-(
Hi.So far, I only tried Altera-SoCFPGA-HardwareLib-GPIO-CV-GNU from Altera web page. Reason for that is because other examples are using the same bootloader. By changing the# ifdef option, I could skip the Calibration procedures (but it leaves the problem in later stage). If my understanding is correct, there is nothing I can adjust/set for failure from Calibration procedure. Anyway, I will try and find other examples available. Thank you.
--- Quote Start --- It seems that helio having their own example rather than than from the altera one, http://rocketboards.org/foswiki/view/documentation/macnicaheliosocevaluationkit --- Quote End --- This is a very, very important distinction. The Helio might have different memory timing, so using an example that is designed for a different evaluation board will most likely fail. I'd recommend comparing the memory timings for the RAM on the evaluation board with the settings in Qsys, or just copy a Helio HPS model in to the Qsys that you are current using and replace the one there. You might need to be careful with the peripheral pin mapping and clocks, though.