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Arria 10 EPCQL Controller

Altera_Forum
Honored Contributor II
1,458 Views

Hi, 

 

I am trying to program my EPCQ-512L from the HPS running Linux. I have the Altera Serial Flash Controller connected from its avl_csr and avl_mem connected to the HPS using the hps2fpga lightweight bridge. I have tried to write the EPCQ and have been successful in writing zeroes. From what I have gathered, I need to erase the sector, then write my values because it erasing sets all the values in the sector to '1'. Here lies my problem; following https://www.altera.com/en_us/pdfs/literature/ug/ug_embedded_ip.pdf , starting on page 153 about the Altera Serial Flash Controller I tried to write to the FLASH_MEM_OP register to erase sectors. I tried writing 0x2 to the register to erase the sector data, but nothing seems to change. I have tried writing other values and from what I can see (when reading the values back from the epcq) there is never a change. I also tried reading the status register to see if there are processes occurring, but it always reads 0. 

Also when I try to read either the FLASH_RD_SID, FLASH_RD_RDID, FLASH_ISR, or FLASH_IMR, the HPS seems to stop responding and I need to reload my .sof. I use either ssh terminal or serial terminal to communicate with my system and when I try to read any of the mentioned registers, the system stops responding on both ssh and serial. I have other signals connected to the lightweight bridge and I have not run into this symptom before. I think this could be part of the problem; maybe the control register is not working at all, but I am not sure where to start debugging this. Any help or points in a direction would be much appreciated. 

 

Thank you in advance :)
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11 Replies
Altera_Forum
Honored Contributor II
379 Views

Hi again, 

 

As an update I still have not gotten it to work. I also tried the Altera Serial Flash Controller II, but I cannot seem to get the erase function to work. I can read the interrupts without my system freezing. What is the difference between Serial Flash Controller I and II. I know that II has more registers than I. I am currently trying to use the Altera ASMI Parallel II IP Core, but I am having the same problem where I cannot get the erase to work properly. It seems that I can read the status register and the flag status register, but I'm not sure if it is working properly because if I read the flag status register after I write the 4byte addressing register, it still reads 0 instead of 1 because of the 4-byte addressing mode enable. Anyone else have problems getting the Serial Flash Controller or ASMI Parallel IP core to work? Is it because I am using the lw hps2fpga bridge to write to the IP core? It seems that it should work in the same fashion as other avalon memory mapped interfaces.  

 

Thank you
Altera_Forum
Honored Contributor II
379 Views

Found the problem. It turns out that the documentation (https://www.altera.com/en_us/pdfs/literature/ug/ug_embedded_ip.pdf) has the WRITE ENABLE BIT marked as reserved! So without the write enable bit, the controller never erases the memory. I found this out by looking at the NIOS driver code that was generated using the bsp editor.

Altera_Forum
Honored Contributor II
379 Views

Hi  

I'm actually confronting the same problem. 

I'm using NIOS to write to EPCQL256 using asmi2. 

Can you be more specific - which bit?? 

can you pinpoint me in the bsp code?? 

 

I'm trying to write to FLASH_MEM_OP to bit 0 and 1. 

did you set a chip select. 

I will be appreciate to any help
Altera_Forum
Honored Contributor II
379 Views

Hi, 

 

Sorry I must have replied too quickly and forgot the details!  

 

For the FLASH_MEM_OP, bit 3 is the write enable bit. First you need to write bit 3 and the sector number, THEN write bits 0 and 1 with the erase command and the sector number. I tried to write the write enable bit and the erase bit at the same time, but that did not work. However, this is all for the Serial Flash Controller II. I am not using asmi2, but according to the documentation, the serial flash controller is just a wrapper over the asmi ip.  

 

For the generated driver code I was talking about, I generated it using the bsp editor and it should be under projectName_bsp -> drivers. The headers and source reg and driver files should be there. However, like I said before, I never tried generating it for asmi II, but I did try using asmi2, but gave up and went back to serial flash controller ii. I am using the HPS to try to program, but wanted figure out if my problem was with my code or the IP so I tried using NIOS.
Altera_Forum
Honored Contributor II
379 Views

I'm going to check it  

Did you use ? 

MEM_BASE or CSR_BASE???
Altera_Forum
Honored Contributor II
379 Views

Do you mean the avl_csr or avl_mem? I used csr base for the erase command and mem base is to read and write to the epcq itself.

Altera_Forum
Honored Contributor II
379 Views

ok 

Can you give an example?? 

I will appreciate - I'm on it for the last week 

Thanks in advance
Altera_Forum
Honored Contributor II
379 Views

Here is a copy pasta of the code from the NIOS driver: 

/* calculate current sector/block number */ sector_number = (block_offset/(epcq_flash_info->sector_size)); /* sector value should occupy bits 23:8 */ mem_op_value = (sector_number << 8) & ALTERA_EPCQ_CONTROLLER2_MEM_OP_SECTOR_VALUE_MASK; /* write enable command */ mem_op_value |= ALTERA_EPCQ_CONTROLLER2_MEM_OP_WRITE_ENABLE_CMD; /* write sector erase command to EPCQ_MEM_OP register to erase sector "sector_number" */ IOWR_ALTERA_EPCQ_CONTROLLER2_MEM_OP(epcq_flash_info->csr_base, mem_op_value); /* sector value should occupy bits 23:8 */ mem_op_value = (sector_number << 8) & ALTERA_EPCQ_CONTROLLER2_MEM_OP_SECTOR_VALUE_MASK; /* sector erase commands 0b10 occupies lower 2 bits */ mem_op_value |= ALTERA_EPCQ_CONTROLLER2_MEM_OP_SECTOR_ERASE_CMD; /* write sector erase command to EPCQ_MEM_OP register to erase sector "sector_number" */ IOWR_ALTERA_EPCQ_CONTROLLER2_MEM_OP(epcq_flash_info->csr_base, mem_op_value); /* check whether erase triggered a illegal erase interrupt */ if((IORD_ALTERA_EPCQ_CONTROLLER2_ISR(epcq_flash_info->csr_base) & ALTERA_EPCQ_CONTROLLER2_ISR_ILLEGAL_ERASE_MASK) == ALTERA_EPCQ_CONTROLLER2_ISR_ILLEGAL_ERASE_ACTIVE) { /* clear register */ /* EPCQ_ISR access is write one to clear (W1C) */ IOWR_ALTERA_EPCQ_CONTROLLER2_ISR(epcq_flash_info->csr_base, ALTERA_EPCQ_CONTROLLER2_ISR_ILLEGAL_ERASE_MASK ); return -EIO; /* erase failed, sector might be protected */ } 

 

I am not sure what type of example you're looking for though...
Altera_Forum
Honored Contributor II
379 Views

Hi Limshutian 

I've changed my bsp - and I have flash specific functions from the BSP like: 

alt_32 altera_epcq_controller2_init(alt_epcq_controller2_dev *flash) 

alt_u32 silicon_id = 0; 

alt_u32 size_in_bytes = 0; 

alt_u32 number_of_sectors = 0; 

 

right now - 

I'm tryng to open device using it's name - i do not get any fd from it. 

 

Did you use it like this? trying to open the device with alt_flash_open_dev??? 

I actually tried to run the example program. 

 

alt_flash_fd* fd; 

int ret_code; 

char source[BUF_SIZE]; 

char dest[BUF_SIZE]; 

/* Initialize the source buffer to all 0xAA */ 

memset(source, 0xAA, BUF_SIZE); 

fd = alt_flash_open_dev("/dev/ext_flash"); 

if (fd!=NULL) 

ret_code = alt_write_flash(fd, 0, source, BUF_SIZE); 

if (ret_code==0) 

{
Altera_Forum
Honored Contributor II
379 Views

I've managed to make it work - I've to uncomment the hal.use_small_foot_print. 

Right now - i'm having the same problem - you saw. 

freezing when erasing sectors 

can you be more specific with "For the FLASH_MEM_OP, bit 3 is the write enable bit. First you need to write bit 3 and the sector number, THEN write bits 0 and 1 with the erase command and the sector number" 

 

This is what I see 

# define ALTERA_EPCQ_CONTROLLER2_MEM_OP_CMD_MASK (0x00000003) 

# define ALTERA_EPCQ_CONTROLLER2_MEM_OP_BULK_ERASE_CMD (0x00000001) 

# define ALTERA_EPCQ_CONTROLLER2_MEM_OP_SECTOR_ERASE_CMD (0x00000002) 

# define ALTERA_EPCQ_CONTROLLER2_MEM_OP_SECTOR_PROTECT_CMD (0x00000003)
Altera_Forum
Honored Contributor II
379 Views

Hello, 

 

I am using Cyclone 10 LP and Altera Serial Flash Controller II IP core. I am using Quartus Prime standard edition, V17.1 In my case also, it hangs when erase function is called. In both of following functions, alt_erase_flash_block and alt_write_flash erase routine is called and hence when I call any of them, it hangs. 

 

In alt_epcq_controller2_erase_block function, I made following change. (remember this is a manual change. Hence if you generate BSP again, this will get lost.) 

 

Instead of following 

/* write enable command */ 

mem_op_value |= ALTERA_EPCQ_CONTROLLER2_MEM_OP_WRITE_ENABLE_CMD; 

I used following: 

/* Unprotect flash. */ 

mem_op_value |= ALTERA_EPCQ_CONTROLLER2_MEM_OP_SECTOR_PROTECT_CMD; 

 

Not sure how it works. But it works! With this, it no longer hangs. (P.S. I got this idea by looking at flash_qspi.c file.) 

 

Perhaps somebody from Intel team might be able to give some insight into this. 

 

Cheers, 

Bhaumik
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