Nios® II Embedded Design Suite (EDS)
Support for Embedded Development Tools, Processors (SoCs and Nios® II processor), Embedded Development Suites (EDSs), Boot and Configuration, Operating Systems, C and C++
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
12453 Discussions

Arria 10 External Memory Interface Pin Infromation

Altera_Forum
Honored Contributor II
1,098 Views

Hi, 

I am using MT41K256M16HA-125 IT:E DDR3 Interface with 10AS016E4F29ISG SoC. 

I had downloaded external memory interface information pin information file and pin out file. I need some clarifications regarding external memory interface.  

 

From the EMI pin information, 

1) which scheme i need to follow (Schemes like 1/2/3/4/5) ? 

2) only pin mapping of address and control lines are given. Could u please suggest a suitable pin mapping scheme for Data Mask, Strobe and Data lines. 

3) From the pin out file, is there any relevance for DQS for X4 / X8/9 etc..in EMI. 

 

Thanks, 

Ninan Mathew 

Sr: Design Engineer. 

 

 

0 Kudos
1 Reply
Altera_Forum
Honored Contributor II
154 Views
Reply