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New Contributor I
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Arria 10 HPS I/O Pin Multiplexing configuration

​The A10 HPS technical reference manual has the following note for each of the pinmux configuration registers (e.g. pinmux_uart0_usefpga) :

"NOTE: These registers should not be modified after IO configuration.  There is no support for dynamically changing the Pin Mux selections"

What is the "IO configuration" referring to here ?   Is it the configuration of the HPS controller for the function using the muxed pins (i.e. UART0 in the case of pinmux_uart0_usefpga ), or something else ?

Thanks !

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New Contributor III

Re: Arria 10 HPS I/O Pin Multiplexing configuration

This refers to the fact that these multiplexing options are determined by the FPGA's programming bitstream (the result of compiling your design through Quartus) and can't be modified by the function of the fabric - i.e. your FPGA code. The function of these pins is fixed for a given FPGA configuration image (bitstream).

 

Cheers,

Alex

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New Contributor I

Re: Arria 10 HPS I/O Pin Multiplexing configuration

Thanks Alex (@a_x_h_75) .  Can I assume that the HPS can update these pinmux configuration registers after the FPGA has started​, but the IO functionality will only work when the HPS configures the same pinmux setup as the FPGA code has been compiled for ?

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New Contributor III

Re: Arria 10 HPS I/O Pin Multiplexing configuration

That's correct. Changing the HPS I/O configuration away from that of the FPGA image will cause issues.

 

Cheers,

Alex