What is the correct way to implement the Arria 10 HPS on-chip RAM to act as my instruction memory for my NIOS II processor.
Currently I’m using an address span extender as a bridge to the fpga-2-HPS port. I set the default offset value of the extender to 0xffe0_0000, the address of the HPS on-chip RAM.
The address span extender slave is at address 0x0 from the NIOS.
I set the reset vector as 0x0000_0000.
Upon building the BSP I get the following error:
SEVERE: Address 0x0 for the CPU Reset vector does not refer to a device connected to it.