Arria 10 with separate hardened DDR controller for PL and HPS

[Altera_Forum]

I have come up with a set of requirements for the memory and I realized my PL memory needs are critical. 

I understand there is a x72 DDR4 hardened PHY+Controller+MPFE in the Arria10 and I'd like to reserve it for the PL.  We will also need external memory access for the Linux O/S running on the HPS. Is there a second DDR hardened PHY+Controller+MPFE that I could use for the HPS?  Eric

[Altera_Forum]

Yes, you can have external memory on both HPS and FPGA, as shown in the attached picture.  

 I encourage you to read the following doc to know more about the I/O bank assignments for the HPS: https://www.altera.com/en_us/pdfs/literature/an/an-a10-soc-device-design-guidelines.pdf

[Altera_Forum]

Is there linux support to access FPGA DDR?

[Altera_Forum]

--- Quote Start ---  Is there linux support to access FPGA DDR?  --- Quote End ---    Are you saying you would like to use HPS to access the FPGA DDR memory over the H2F bridge? Right now I don't think the HPS can support 2 memory controller instances (one in its own HPS DDR and the other FPGA memory) - besides, it would be quite inefficient to do it over the H2F bridge. I believe letting the FPGA access the HPS DDR over the F2S bridge is a better alternative.