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PHJ
New Contributor I
2,732 Views

Arria10 HPS Memory Controller Register Documentation

I am looking through the UEFI HPS boot code that is performing​ memory controller initialization (ConfigureHmcAdaptorRegisters).

It is accessing registers with a base address of 0xffcfa000 (ALT_IO48_HMC_MMR_OFST).

I do not see any registers at this location in the Intel Arria10 Hard Processor System Technical Reference Manual (a10_5v4|2017.07.22).

Can someone please point me to where I can find the description of these registers ?

 

Looking at the history of this reference manual, it appears as though the data I am looking for was removed back in May2017 - does anyone know why?

 

From May2017 entry in System Interconnect Revision History:

Remove io48_hmc_mmr Address map and registers from System Interconnect Address Map and Register Definitions section

 

Thanks !

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7 Replies
KennyT_Intel
Moderator
49 Views

Seems like it mention it is not supported.

 

May 20172017.05.31Removed HMCREGS row from HPS Peripheral Region Map table. Accesses to this address block are not supported.

PHJ
New Contributor I
49 Views

​Why is the Intel UEFI Boot Loader code using these registers then ?

 

There must be something implemented as these registers seem to be at the root of configuring the memory controller.

 

The ConfigureHmcAdaptorRegisters routine:

  • reads the NIOSRESERVE0 register to determine DramIoWidth
  • reads the CTLCFG1 register to determine if ECC is enabled

The ConfigureDdrSchedulerControlRegisters routine:

  • reads the CTLCFG1 register to determine DramAddrOrder
  • reads the DRAMADDRW register to determine col/row/bank width information
  • reads the DRAMTIMING0, CALTIMING0, CALTIMING1, CALTIMING2 and CALTIMING9 registers to determine DDR timings
  • reads the CTLCFG0 register to determine burst len and timing
  • based on the above registers the ALT_NOC_MPU_DDR_T_... registers are configured

The GetPhysicalDramSize routine:

  • reads the DRAMADDRW register in calculation to determine returned DRAM size

The DisplayMemoryInfo routine:

  • reads the DRAMADDRW, CTLCFG0, NIOSRESERVE0 and NIOSRESERVE1 registers and prints the contents

 

On my dev board I see the following from DisplayMemoryInfo for the IO48_HMC_MMR registers:

        HMC_MMR_DRAMADDRW: 0x000049EA

                column address width          : 10 bits

                row address width             : 15 bits

                bank address width            : 2 bits

                bank group address width      : 1 bits

                chip select address width     : 0 bits

                Memory Size                   : 1073741824

        HMC_MMR_CTLCFG0: 0x08421011

                Memory Type                   : DDR4

        IO48_HMC_MMR_NIOSRESERVE0: 0x00000620

        IO48_HMC_MMR_NIOSRESERVE1: 0x00004800

 

How is the memory controller configuration in the Intel UEFI boot code working if accesses to the ALT_IO48_HMC_MMR address block are not supported ?

PHJ
New Contributor I
49 Views

​Hi -

 

Can @KennyT_Intel​  or someone else from Intel please look at the above reply ?

How is the memory controller configuration in the Intel UEFI boot code working if accesses to the ALT_IO48_HMC_MMR address block are not supported ?

 

Thanks,

 

Paul

KennyT_Intel
Moderator
49 Views

Ya, I am looking into it..

KennyT_Intel
Moderator
49 Views

Due to security reason, we dont expose those registers to customers. There is a handshake that occurs between the HPS and the CPU inside the memory controller column but we don’t document. If we exposed those registers without a programming model, that would expose sequencing issues if we allowed customers to access those registers directly.

 

There is no really any status register besides calibration pass/fail that is exposed by that interface. That interface is mostly used to configure the various controller timing registers and settings, which is done automatically by the boot process based on the settings in the memory controller GUI.

PHJ
New Contributor I
49 Views

​Hi @KennyT_Intel​ 

 

Thanks for the response.  The reason I started looking at this was that I wanted to enable ECC for the DDR and was looking at what the UEFI reference design did for this.

The UEFI code is checking the CTLCFG1_CFG_CTL_EN_ECC_GET bit from the ALT_IO48_HMC_MMR_OFST register to determine whether to enable the ECC.

I need to understand what this bit is indicating and how I can affect it and was looking for a description of this register/bit to help.  On our A10 dev kit running with the supplied DDR4, this bit is not set and the ECC is not being enabled.

Can you provide further insight into this please ?

 

Thanks !

 

Paul 

 

KennyT_Intel
Moderator
49 Views

Well. you can enable ECC in DDR4 IP directly then regenerate IP and recompile design.

Quartus should help to take care of all the backend processing.

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