Hello,According to the ArriaV SoC Reference Board doc (MNL-01080-1.1), the ENET_HPS_INTN is connected to A18 (p.2-26). But, the A18 pin is a dedicated pin for the RGMII0_TX_CTL (EMAC0, which is not in use according to GHRD ghrd_5astfd5k3). So, how should it exactly work? Is the connection correct? According to the GHRD ghrd_5astfd5k3, the EMAC0 is not in use, so why the on-board signal ENET_HPS_INTN, which is related to EMAC1, connected there? Thank you!
no idea if we have design example for Arria V before. But you might consider to open up the RGMII design example that belongs to cyclone V for configuration reference to your Arria V..