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Altera_Forum
Honored Contributor I
1,997 Views

Avalon 8 bit with Nios 32 bit possible?

It is possible to create a component (ex. UART) with avalon MM slave interface with 8 bit data width and use it with Nios II with 32 bit bus? 

I tried and compile fine but Nios II don't start on real fpga.. 

 

Thank you
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11 Replies
Altera_Forum
Honored Contributor I
44 Views

Yes, it is possible. It should work fine.

Altera_Forum
Honored Contributor I
44 Views

Tricks was that instead of IORD and IOWR, 8 bit version IORD_8DIRECT and IOWR_8DIRECT should be used ;)

Altera_Forum
Honored Contributor I
44 Views

However, in practise, you don't want to do it. 

Instead create a 32bit slave that ignores the high bits on writes and returns zeros on reads. 

Remembering to look at the byte enables. 

 

If you have an 8bit slave you'll get a bus width adapter added than generates 4 cycles to your slave for every access done by the nios. 

 

Also, since the nios always asserts all 4 byte enables on reads, the data fifo probably work work properly.
Altera_Forum
Honored Contributor I
44 Views

Thank you for your tips, i'm in a learning stage for qsys systems

Altera_Forum
Honored Contributor I
44 Views

 

--- Quote Start ---  

 

If you have an 8bit slave you'll get a bus width adapter added than generates 4 cycles to your slave for every access done by the nios. 

 

--- Quote End ---  

 

 

This is incorrect (perhaps old?) information. 

 

8/16/32-bit accesses from NIOS via IORD/WR_xxDIRECT() behave like you would naturally expect against an 8-bit slave: you get 1, 2, or 4 transactions.
Altera_Forum
Honored Contributor I
44 Views

As as far as I know the nios always asserts all 4 byte enables on reads - and discards the unwanted bytes later. 

The bus width adapters are also well known for generating master cycles with no asserted byte enables. 

If you also end up with a clock crossing bridge the transfers get very slow indeed.
Altera_Forum
Honored Contributor I
44 Views

 

--- Quote Start ---  

As as far as I know the nios always asserts all 4 byte enables on reads - and discards the unwanted bytes later. 

The bus width adapters are also well known for generating master cycles with no asserted byte enables. 

If you also end up with a clock crossing bridge the transfers get very slow indeed. 

--- Quote End ---  

 

 

While it may be possible to create a broken system as you describe, or possibly it was a rule of thumb with older tools --- at least with Qsys your described behavior is not true. I think it must "work correctly" since Quartus 12 as that is where I implemented a bursting 8-bit slave and didn't run into the issue at that time. 

 

To test it again, I just created a dummy system in 14.0 with 8/16/32-bit slaves and a NIOS running this program: 

int alt_main(void) { for(;;) { IORD_8DIRECT(SLAVE_8BIT_BASE, 0x10); IORD_8DIRECT(SLAVE_16BIT_BASE, 0x10); IORD_8DIRECT(SLAVE_32BIT_BASE, 0x10); IORD_16DIRECT(SLAVE_8BIT_BASE, 0x10); IORD_16DIRECT(SLAVE_16BIT_BASE, 0x10); IORD_16DIRECT(SLAVE_32BIT_BASE, 0x10); IORD_32DIRECT(SLAVE_8BIT_BASE, 0x10); IORD_32DIRECT(SLAVE_16BIT_BASE, 0x10); IORD_32DIRECT(SLAVE_32BIT_BASE, 0x10); } }  

 

Attached is the waveform.  

You'll see the 8-bit slave correctly get hit for 1/2/4 transactions. 

You'll see the 32-bit slave correctly get hit for 1 transaction with 1, 2, or 4 byteenables set. 

You'll see the 16-bit slave correctly get hit for one or two transactions with 1 or 2 byteenables set. 

 

 

In other words, it all kind of works like you would expect for a processor with dedicated byte/halfword/word {load,store} instructions and at least Qsys by default doesn't break anything.
Altera_Forum
Honored Contributor I
44 Views

It actually looks as though the bus width adapter is asserting 'byte enable' but not asserting 'read' during the extra cycles. 

 

The nios is definitely documented as always doing 32bit reads (ie asserting all 4 byte enables) 

Of course that might have changed - I don't remember us tracing them.
Altera_Forum
Honored Contributor I
44 Views

Attached is updated waveform with the NIOS data master Avalon signals expanded, where you'll see it is correctly issuing reads with 1,2,4 bytes enabled; the bus width adapter isn't doing much if anything. 

 

Where do you see that the NIOS is definitely documented as always doing 32-bit access? The instruction set reference (ldbuio, ldhuio, ldwio) is pretty clear on what it is advertising, and I tend to agree with it based on my experiences.
Altera_Forum
Honored Contributor I
44 Views

Try using signaltap to look at a real nios rather than using the simulator, or at least run the gate-level simulator talking to avalon slaves. 

TCM is read every clock regardless of the instruction type. 

 

I can't find the actual note about reads, but under 'Data Master Port' in Chapter 2 of the processor reference (page 2-11 in the 9.0 version I've got an 'dead tree') it states "Byte-enable signals on the master port specify which of the four byte-lane(s) to write during store operations." - nothing is mentioned about reads.
Altera_Forum
Honored Contributor I
44 Views

Byte-enables are usually used during writes, asserting all high for writing words, partly for halfword and byte. 

 

Nios does toggle the byteenable for reads but it stills reads 32-bit word. The byteenable can be used by the slave for byte-lane enabling depending on the slave use case. For example, the Onchip-Memory uses byte-enable for word/partial write but always returns 32-bit data for read. 

 

Qsys interconnect should help to perform data width adaptation to match the master-slave interfaces.
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