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Altera_Forum
Honored Contributor I
1,225 Views

Avalon CAN controller IP from Opencores

I know that this question has made before. But I would like to know if someone implemented an Avalon based ip for the CAN controller from Opencores http://opencores.org/project,can. The opencores version is on Wishbone. I think it is mentioned that there was a version in the past on Niosforum but I cant find anything. It would be really useful if somene who made the bus connection can share the IP. Thanks:

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5 Replies
Altera_Forum
Honored Contributor I
31 Views

If you look at the timing diagrams for wishbone and Avalon, you will find that they are very close. You should be able to modify the wishbone version to work with Avalon.

Altera_Forum
Honored Contributor I
31 Views

 

--- Quote Start ---  

If you look at the timing diagrams for wishbone and Avalon, you will find that they are very close. You should be able to modify the wishbone version to work with Avalon. 

--- Quote End ---  

 

 

Could you recommend something like a tutorial how this modification can be done. I've never made something similar in the past and I don't know where to start.
Altera_Forum
Honored Contributor I
31 Views

I haven't seen any tutorials on this, but it would make a nice project to learn HDL coding. I'd start with simulation. Here is a forum post with more info http://opencores.org/forum,cores,0,863

Altera_Forum
Honored Contributor I
31 Views

Followin thuis post http://www.alteraforum.com/forum/showthread.php?t=39783 there is a wrapper already been made for this purposse. Ive compiled the files and works fine. The problem that I have is to attach the signals in qsys when I create a new component. So a first question is in which interface should CAN interface signals attached? 

 

// CAN interface input CAN_clk, input CAN_reset, input CAN_rx, output CAN_tx, output CAN_bus_off, output CAN_irq, output CAN_clkout
Altera_Forum
Honored Contributor I
31 Views

Use a conduit. Then you can export the conduit interface in your QSys system to connect those signals to ports on the QSys generated component.

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