Nios® II Embedded Design Suite (EDS)
Support for Embedded Development Tools, Processors (SoCs and Nios® II processor), Embedded Development Suites (EDSs), Boot and Configuration, Operating Systems, C and C++
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
12409 Discussions

Avalon Interface -> burst transaction

Honored Contributor II

Hi all,  


I have a question regarding the Avalon Interface…  


As for the burstcount lines, does it indicate the number of bytes/words/transactions on the writedata bus? Lets’s say the writedata has 256 lines. So, if is drive the burstcount with value 0x8, does it mean that the burst should contain 8 transactions of 256 bits each one (totally 256 bytes would be moved)?  


As for the address lines, should they indicate a byte address for the first byte in the burst?  


Thank you!
0 Kudos
1 Reply
Honored Contributor II

It is easier to understand the Avalon-MM protocol if you see it in action. Take a look at post#25 here: 


Download the BFM example, and run it. 


Actually, it looks like I wrote a tutorial too ... see the first link here