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Altera_Forum
Honored Contributor I
959 Views

Avalon MM Slave Query

Hey Everyone, 

 

For a university project I'm trying to implement a custom hardware block to help accelerate the calculation of the determinant of a matrix. 

 

We're using Quartus V12, and a TerASIC DE0 board 

 

We've implemented this Avalon Memory Mapped Slave (google "avalon slave interface block" I'm not allowed to post links yet") into our NIOS block in Qsys with only 10 registers, due to 16 giving us naming convention errors, but have solved by editing the tcl file. We have the 10 registers enabled for write/read and have connected register 0-in to register 0 out just to test writing and reading to the registers. We are testing it by writing to the register 0 and then reading it again. 

 

We can get it to work if we offset the base address to the memory map by 52? but read from the base address.  

 

for(i=0; i<3; i++){ 

IOWR_32DIRECT(SLAVE_MM_BASE+52, 0, number[i]); 

 

wait_time = IORD_32DIRECT(SLAVE_MM_BASE, 0); 

 

printf("%x \n",wait_time); 

 

Does anyone know of a reason for this, its not a huge problem if not as we can get by just offseting by 52, but it would be nice to know the reason why, the number doesn't seem very logical IMO. if its to do with the registers from the custom logic being at the base address why isn't the offset 40? (4 bytes per word x 10 words) 

 

If anyone also has a suggestion for using a different method for memory mapping to custom logic I would appreciate any input. 

 

Many Regards 

 

Tom
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5 Replies
Altera_Forum
Honored Contributor I
54 Views

No there shouldn't be any offset between the read and write addresses. Could you share your HDL code? I don't really get what you are saying here: 

 

--- Quote Start ---  

We've implemented this Avalon Memory Mapped Slave (google "avalon slave interface block" I'm not allowed to post links yet") into our NIOS block in Qsys with only 10 registers, due to 16 giving us naming convention errors, but have solved by editing the tcl file. 

--- Quote End ---  

What kind of naming convention errors, and what did you need to edit in the tcl file? Creating a component with 16 registers shouldn't be a problem.
Altera_Forum
Honored Contributor I
54 Views

The error we got was "Error (275046): Illegal name "slave_mm_io_datain_119" -- pin name already exists" we get this for a number of other pins. Reasoning being that the bit number is just appended to the register number, therefore confusing register 1 bit 19 with register 11 bit 9. By going into the tcl and changing "user_datain_10" to "user_datain_a" and so on this resolved itself.  

 

We're using schematic capture with this just to quickly test functionality, with our custom logic going to be writen in verilog. Attached are the original tcl and verilog files and our schmatic layout. 

If we now write to the registers in one order we expect to read back with the numbers reversed, due to the wiring. 

 

However what we get is a 0's from register 0 to 11 and then a block of 4 of one number then 0's the rest of the way down. we sent 2 numbers and alternated them. 

 

any suggestions?
Altera_Forum
Honored Contributor I
54 Views

Your code isn't really easy to follow... but I see that you have in fact 4 different registers for each port, so you shouldn't read back at the same address that you are writing to. If I can understand this correctly, to write to your output 0 you need to write to register 1, but to read back the input 0 you need to read register 0. 

Anyway I suggest to put up some Signaltap probes in your component and try to figure out what is happening, it is difficult to do with just looking at the code. 

Is there a reason why you need so many pipelining stages to read back the input ports?
Altera_Forum
Honored Contributor I
54 Views

This is just initial testing to get our heads around how the registers work, we will at the next stage have our logic in there and the outputs from that going into the registers. 

 

What we what to do is send an address and some control signals in a bit field from NIOS to our custom logic, which will then go away perform the operation. Is this slave the best way of doing it, or is there a better slave unit?
Altera_Forum
Honored Contributor I
54 Views

If you plan to put your custom logic outside of the SOPC/QSYs system, it may be easier to just use GPIO components to control it. If you plan to integrate everything inside a custom component, then just use some vector registers that are accessed by both the avalon side and your custom logic.

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