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Altera_Forum
Honored Contributor I
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Avalon-MM Tristate Bridge and custom component

Hello, 

 

I have made a design with Avalon-MM Tristate Bridge connected to a Common Flash Interface Controller (CFI) and a custom component (see https://www.alteraforum.com/forum/attachment.php?attachmentid=4775 ). Both connected to the same 80 MHz clock (12,5ns periode). 

 

The custom component and the CFI flash are sharing data/address/read_n/write_n. The chipselects are not shared. 

 

As you can see in “Description custom component:“. I want a holdTime 50ns, setupTime 50ns and a WaitTime 200ns. These parameters are also used for the Common Flash Interface Controller. Then I measure the chipselect/read signal with a scope connected to the Common Flash Interface Controller, all is working well. But the data was not correct! So I added SignalTap to see what was wrong on the interface.  

 

I used the command in the nios2 terminal: “nios2-flash-programmer --base=0x0 -R readback.bin –debug”. To see what is happening (see https://www.alteraforum.com/forum/attachment.php?attachmentid=4821 . At the trigger line you can see a data value of A8h. This is not the value I expected, I was expecting the value 34h. The value is there but the “nios2-flash-programmer” is tells me that read a value of A8h (you can see in “Error logging from nios2-flash-programmer:“. The next value I expect is also a 34h, but the “nios2-flash-programmer” tells me a value of 09h is read. This is also visible in the SignalTap image.  

 

There is some think wrong with reading the data. I do not understand this. Can anyone help me with my problem. 

 

I'm using quartus 10.1 SP1 with a cyclone 4 device. 

 

Error logging from nios2-flash-programmer: 

Using cable "USB-Blaster ", device 1, instance 0x00 Resetting and pausing target processor: OK No CFI table found at address 0x00000000 Original contents (after writing 0xF0 and 0xFF to address 0x00000000): 0: A8 09 00 04 A8 09 00 04 A8 09 00 04 A8 09 00 04 ................ 10: A8 09 00 04 A8 09 00 04 A8 09 00 04 A8 09 00 04 ................ 20: A8 09 00 04 A8 09 00 04 A8 09 00 04 A8 09 00 04 ................ 30: A8 09 00 04 A8 09 00 04 A8 09 00 04 A8 09 00 04 ................ 40: A8 09 00 04 A8 09 00 04 A8 09 00 04 A8 09 00 04 ................ Contents after writing 0x98 to address 0x000000AA: Same after writing 0x0098 to address 0x00000154: Same after writing 0x00000098 to address 0x000002A8: Same after writing 0x98 to address 0x00000055: Same after writing 0x0098 to address 0x000000AA: Same after writing 0x00000098 to address 0x00000154: Same after writing 0x98 to address 0x00000154: Same after writing 0x0098 to address 0x000002A8: Same after writing 0x00000098 to address 0x00000550: 0: A8 09 00 04 A8 09 00 04 A8 09 00 04 A8 09 00 04 ................ 10: A8 09 00 04 A8 09 00 04 A8 09 00 04 A8 09 00 04 ................ 20: A8 09 00 04 A8 09 00 04 A8 09 00 04 A8 09 00 04 ................ 30: A8 09 00 04 A8 09 00 04 A8 09 00 04 A8 09 00 04 ................ 40: A8 09 00 04 A8 09 00 04 A8 09 00 04 A8 09 00 04 ................ Ignored possible autoselect code A8-A8 as no override data present in section Ignored possible autoselect code 09A8-09A8 as no override data present in section Leaving target processor paused  

 

Description custom component: 

set_module_property DESCRIPTION "" set_module_property NAME comp_eb_pld set_module_property VERSION 1.0 set_module_property INTERNAL false set_module_property OPAQUE_ADDRESS_MAP true set_module_property GROUP own set_module_property AUTHOR "tja" set_module_property DISPLAY_NAME comp_eb_pld set_module_property TOP_LEVEL_HDL_FILE "" set_module_property INSTANTIATE_IN_SYSTEM_MODULE false set_module_property EDITABLE true set_module_property ANALYZE_HDL TRUE add_interface avalon_tristate_slave avalon_tristate end set_interface_property avalon_tristate_slave activeCSThroughReadLatency false set_interface_property avalon_tristate_slave addressAlignment NATIVE set_interface_property avalon_tristate_slave explicitAddressSpan 0 set_interface_property avalon_tristate_slave holdTime 50 set_interface_property avalon_tristate_slave isMemoryDevice false set_interface_property avalon_tristate_slave isNonVolatileStorage false set_interface_property avalon_tristate_slave maximumPendingReadTransactions 0 set_interface_property avalon_tristate_slave printableDevice false set_interface_property avalon_tristate_slave readLatency 0 set_interface_property avalon_tristate_slave readWaitStates 200 set_interface_property avalon_tristate_slave readWaitTime 200 set_interface_property avalon_tristate_slave setupTime 50 set_interface_property avalon_tristate_slave timingUnits Nanoseconds set_interface_property avalon_tristate_slave writeWaitStates 200 set_interface_property avalon_tristate_slave writeWaitTime 200 set_interface_property avalon_tristate_slave ENABLED true add_interface_port avalon_tristate_slave ats_eb_pld_data data Bidir 8 add_interface_port avalon_tristate_slave ats_eb_pld_address address Input 8 add_interface_port avalon_tristate_slave ats_eb_pld_chipselect_n chipselect_n Input 1 add_interface_port avalon_tristate_slave ats_eb_pld_read_n read_n Input 1 add_interface_port avalon_tristate_slave ats_eb_pld_write_n write_n Input 1
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Altera_Forum
Honored Contributor I
48 Views

major update in tests performed!

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