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Altera_Forum
Honored Contributor I
1,277 Views

Avalon MM slave register mapping in VHDL

Hi, 

 

I am a little bit confused on how the avalon memory mapping works. I hope someone can clarify this for me. 

 

I created a mm slave in VHDL. Which seems to work fine when accessed from the NIOS. At least for one register. But I don't understand how the addressing works if I use more registers. I thought that it is kind of like writing in the ram from the NIOS and the VHDL component then can read that ram? But if that were the case then there should me some kind of mapping that maps my VHDL variables to a specific ram address? I couldn't find something like that. 

 

Or does it work more like a real bus? A have an address line and a data line and then have to check the address and put the data manually in a VHDL variable? But where is the memory mapping here? 

 

As I said I am confused. Maybe someone can point me in the right direction. 

 

Best Regards
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2 Replies
Altera_Forum
Honored Contributor I
101 Views

Yes it works like a real bus. You need to implement the address decode logic within your component.  

 

Your module will have a base address which is set from within Qsys when you instantiate your component and attach it to the NIOS data bus, and your individual registers will have offsets from the base address determined by you when you create the address decode.
Altera_Forum
Honored Contributor I
101 Views

Thanks, I think I understand it now.

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