I have a design running on the Cyclone dev. kit with one read master and one write master to SRAM. Code and data is in SDRAM.
The read master is Lancelot VGA IP, and the write master is my own IP core for writing data to the VGA framebuffer (fast rectangles).
I simulate the design with test code in Modelsim with perfect results, and each core works in hardware, but
not simultaneously. When compiling both cores into hardware, I can download code to the board, but the processor seem stalled. Some compilations results in disability to download code to the board.
SignalTap shows me that all master signals are inactive (low) when not in transfer mode (correct i hope). The Avalon bus manual does not say much about how signals should be when not in transfer mode.
Does anyone have any hint to what this is?
Martin
