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Altera_Forum
Honored Contributor I
978 Views

Avalon native and dynamic addressing

Hi all! 

 

 

I've already seen some discussions about native and dynamic addressing and interfacing peripherials with fewer address width. But this is still a bit confusing to me since there are mismatches between answers to similiar topics and the documentation. 

I'm trying to attach the 8-bit I2C core from OpenCores to my NIOS-based system in Quartus 15.0 with QSYS. There are no byte-enable signals in this core and I thought I don't need it because I'm using native addresing and all byte-enables will be '1' anyway. Then I read that in newer versions (since 12.0) it is not recommended to use native addresing and I need to add byte-enable capability to the original core. But some people saying that it's better just to build 32-bit peripherial and don't care for 32..8 bits. But how to control type of addresing?? I can see it in .sopcinfo xml and it is automatically set to "dynamic" for my I2C. 

So what is the proper and best way to connect such peripherial in QSYS last versions and how can I handle this addresing type issue? 

 

 

Thanks in advance!
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Altera_Forum
Honored Contributor I
32 Views

The type of addressing is controlled in a file with extension *_hw.tcl, which is used to describe and represent the core in Qsys. You should stick to dynamic as native addressing support is obsoleted.  

 

Using the io.h to access the 8 bits interface of the I2C should be fine, you can use IORD/WR_8DIRECT. Qsys can help with the width adaptation.
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