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Altera_Forum
Honored Contributor I
741 Views

Best way to share DDR w/ FPGA

I have a rather simple task to perform but I don't know where to start. 

 

I'm using a Cyclone V SoCKit board. 

 

What I want to do is have the ARM processor write a data table in DDR so that the FPGA can later come in an read it. 

 

I'd prefer to not use DMA or any complicated mechanism.  

 

Is there a way to do this within QSYS? I've played with the simple bridge for programmed I/O but I need a little more. 

 

Can anyone point me in the right direction? 

 

Thank You, 

Jon Herr
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7 Replies
Altera_Forum
Honored Contributor I
29 Views

A DMA is probably the easiest way to go. 

Another way to do it would be to use a double port on-chip RAM. One port would be connected to a slave interface to the ARM processor and the other port to your FPGA logic module.
Altera_Forum
Honored Contributor I
29 Views

Thanks for the reply. 

 

Would it be possible to an "external bus to avalon bridge" as listed in the university program IP area? The signals look exactly like what I want but when I connect the modules together I have memory address mapping conflicts that I don't know how to resolve. 

 

I can't use the on chip RAM because I need more storage space for my data table.
Altera_Forum
Honored Contributor I
29 Views

If the data you want to transfer is a (or a group of) memory block, I think the easiest solution would be to use the SGDMA or the modular SGDMA component. When configured as memory-to-stream, they deliver the data on an Avalon Stream Source interface which is very easy to use. Just put 'ready' to 1 when you can receive data, and when 'valid' is 1, you have new data on the 'data' signal.

Altera_Forum
Honored Contributor I
29 Views

hi!! 

my question: What do you mean with a Data table? Its a lot of Data? Should be fast? It changes or your going to write just one time on memory? 

-For a lot of data and fast: Reserved memory using kernel parameters (use the uboot source file) 

-For some data (changing): DMA 

-For some Data (ones): Onchip RAM 

..... 

depends!!!! 

regards  

c
Altera_Forum
Honored Contributor I
29 Views

Murillo: It's up to 4 GB of data that can be updated by the user at any time. Will be 8GB in the final design. This pushes me in to DDR for more space. Output speed is less than 50 megabits per second... so not fast at all compared to DDR storage of the table. 

 

Daixiwen: I think I have the modular SGDMA component installed but my next question is - how do we access this from the CV ARM processor? All of the driver examples I find are written for NIOS. 

 

There is one for CV but how the scatter / gather driver made it in to the kernel is not clear.  

 

I'm using an Atlas / De0-Nano-SoC board. 

 

Regards,  

Jon
Altera_Forum
Honored Contributor I
29 Views

I'm sorry but I have no experience in using those components from an ARM processor, but the principle should be the same than when using a NIOS CPU.

Altera_Forum
Honored Contributor I
29 Views

Hi!! 

Well thats alot of data andyour implementation should be fast (I think!)  

I dont know if DMA is a good idea!  

Better: http://forum.rocketboards.org/t/how-to-reserve-ddr3-memory-region-for-fpga-direct-access/162/2 

But maybe you can try both and compare them!!  

keep us ...updated!! 

bye
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