Boot fails from EPCS

[KAbde4]

Actualy I’m using hardware card based on Cyclone 10LP FPGA for my project.

 I'm using to try to develop a small test program. on the platform designer i used the "Serial Flash Controller Intel FPGA IP" to boot from EPCS16.

I create the .sof file and .hex files as detailed in the manuals and program the flash with a .jic file (As mode), the FPGA appears to configure correctly (blinking of led) but no sign that the NIOS is running. I already look on the forums the similar problem and I followed your advice but no solution.

Quartus : V 18.1 prime lite edition

FPGA : Cyc 10 LP

Memory: EPCS16

MSEL : Standard 011

epcs clk : 20 Mhz

NIOS clk : 90 Mhz

NIOS II Core : Nios II e

can you help me to solve this issue? 

best regards

[AnandRaj_S_Intel]

Hi,

Re-Check the steps and file used for creating .jic.

Attached the example project. compare the map file for debugging.

If possible please attach the .map, .sof and .hex file.

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Regards

Anand

[meenalkb]

Hi, I am in a similar position, trying to boot from EPCQ memory. I tried this example you attached, but you haven't set the .text section to PERIPHERALS_EPCQ64_AVL_MEM. So this example doesn't apply for Execute-in-Place, is that correct?

[KAbde4]

Hi ARS I add that when I load just the .sof and run the application via Eclipse, the system is working correctly. Attached the files requested Best Regards

[KAbde4]

posted a file.

[AnandRaj_S_Intel]

​Thanks,

Configuration device used? (EPCQ part Number)

[KAbde4]

Thank you for your reply; The configuration device used is EPCS16 Best regards

[AnandRaj_S_Intel]

​Hi,

Please test attached file.

 Steps:

1. Select programming file type .jic
2. Select flash device EPCS16
3. Add flash device 10CL025Y
4. Add sof file
5. Add hex page and file
6. Click on SOF data ->click properties ->select page=Page 0 and address mode=auto
7. Click on .sof file ->properties ->enable compress option
8. Click on HEX data->properties ->select relative address and set it =0x08000
9. Click generate

Regards

Anand

[KAbde4]

Hi , I loaded the file .jic, unfortunately it is the same case as before. Best Regards

[KAbde4]

and FPGA does not configure properly Best regards

[AnandRaj_S_Intel]

​Hi,

Try below file.

1. Click on SOF data ->click properties ->select page=Page 0 and address mode=start
2. Click on HEX data->properties ->select relative address and set it =auto

Regards

Anand

[KAbde4 · Accepted solution]

Hi I followed these steps, but I modified the second. “2. Click on HEX data->properties ->select absolute addressing” instead of “Click on HEX data->properties ->select relative address and set it =auto” and also putting the right address on reset vector offset now the NIOS boot correctly. Thank you Anand for your help. Best regerds