Booting Nios from EPCS flash controller

[Altera_Forum]

Hi All, 

I was working on a project with Nios cpu and 8Gb DDR2 memory. the design was done and working properly booting on the DDR2. then I tried to boot the Nios from the EPCS flash, but it did not work at all. below is the Qsys address assignment:  http://www.alteraforum.com/forum/attachment.php?attachmentid=11056&stc=1  I have the experience of booting the Nios CPU from the EPCS flash, but it is not working this time. but I think it could be the instruction master address range has exceed 28 bit as the address of the EPCS flash controller started from 0x50001000. looking for you opinions, thank you very much.  Best Regards Daniel

[Altera_Forum]

You are still within the 2GB region (31-bits), so it should work. 

Did you assign the reset vector the EPCS controller? What version of Quartus are you using?

[Altera_Forum]

First, which controller are you using? the legacy EPCS controller, or the new Altera Serial Flash controller? 

For the legacy one, you should set NIOS II reset vector to EPCS controller, with 0x0 offset. For the new one, you should point NIOS II reset vector to EPCS, with reset vector offset value, which should not be 0x0. You need to consider the .sof size. So the JIC file will be like this (just an example)  harware.sof 0x00000000 to 0x00fffffe software.hex 0x00ffffff to 0x02776760