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Altera_Forum
Honored Contributor I
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Booting from on-chip memory works, but resets every few seconds

In Qsys, I have the cpu reset and exception pointing to a 32-bit wide 28k onchip ram. The linker setting for the nios app has everything pointing to the same onchip ram. 

 

At the moment, the on chip app code (7k code+initialized data, 21k stack/heap) that's synthesized into the logic design, consists only of: 

 

 

// Init System 

alt_irq_init (ALT_IRQ_BASE); 

ALTERA_AVALON_TIMER_INIT ( TIMER1_SYSTEM_500US, Timer1_System_500us); 

 

ALTERA_AVALON_TIMER_INIT ( TIMER2_GENERAL_1MS, Timer2_General_1ms); 

ALTERA_AVALON_SYSID_QSYS_INIT ( SYSID, sysid); 

 

// Init UART 

IOWR_ALTERA_AVALON_UART_CONTROL(UART_DEBUG_BASE, 0x0000); // inhibit all UART IRQ sources 

//alt_ic_isr_register(UART_DEBUG_IRQ_INTERRUPT_CONTROLLER_ID, UART_DEBUG_IRQ, DBG_ISR, &context_dbg_uart, 0x00 ); 

IOWR_ALTERA_AVALON_UART_DIVISOR(UART_DEBUG_BASE, (ALT_CPU_FREQ/DEFAULT_BAUD_RATE_115200) + 1); 

 

// Reset Status/Error Flags 

IOWR_ALTERA_AVALON_UART_STATUS(UART_DEBUG_BASE, 0); 

IOWR_ALTERA_AVALON_UART_CONTROL(UART_DEBUG_BASE, ALTERA_AVALON_UART_CONTROL_RRDY_MSK ); 

 

 

 

IOWR_ALTERA_AVALON_UART_TXDATA ( UART_DEBUG_BASE , '1' ); 

 

 

while ( 1 ) 

while ( 0 == ( ALTERA_AVALON_UART_STATUS_TRDY_MSK & IORD_ALTERA_AVALON_UART_STATUS ( UART_DEBUG_BASE ) )); 

IOWR_ALTERA_AVALON_UART_TXDATA ( UART_DEBUG_BASE , '2' ); 

usleep ( 1000000 ); 

 

 

 

When I power-on, I see the '1' across the RS-232, and then the '2', but a second later, I see the '1' again, and the reset led indicator toggles. I'm thinking some (instruction?) exception is being thrown, or perhaps some kind of stack overflow corruption is going on, but I can't find anything unusual.. nor any way to pinpoint what exactly is causing the reset. 

 

Any ideas?
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