I'm trying to do the seemingly simple task of putting the nios code in fpga ram blocks, and at power-on, the bootloader should copy the code from on-chip memory to external sram.In the sopc I have the cpu's reset vector pointing to on-chip memory, with the nios ide set to external sram for the prog .text. Since the code and the bootloader need to be in internal ram at power-on, I use elf2hex to convert the resulting elf file, however it is not correct... it's only 2kb, where it should be the full code + the bootloader (or around 45kb). It works if in the nios ide points the .text to on-chip ram. Then the elf2hex file has the application code correct and can be used during synthesis to create a system that boots and executes from on-chip ram. But how can I have the code reside in on-chip ram, and yet also have the bootloader (also in on chip ram) *COPY* the program code over to sram and execute from there?
A carefully crafted linker script should let you link most of your code to run from the SRAM address (while being loaded into the internale memory), then just add a small piece of code at the reset vector to copy the code to SRAM.But I do wonder why you want to do this. If your code fits in internal memory then I would make it a tightly coupled instruction memory and execute from there - removing the i-cache. Unless you are later using the memory for something which has to be internal.