CFI Flash doesn't read correcty after reset

[Altera_Forum]

I have a Stratix II GX with 2MBytes Flash in 8 bit mode and 512kBytes SRAM in 8 bit mode. 

 The Flash memory is hooked up properly, in that most of my applications run just fine, but I'm having trouble with one FPGA configuration. With the same build of FPGA I can generate one BSP 8.1 and application and load it into flash memory with the nios2-flash-programmer and everything works, it restarts properly after power cycling and it restarts properly on pressing the reset button.  Unfortunately with the same BSP in version 9.0 I can program the flash memory as before and I can run my program and all works well, but then when I press the reset button it reads garbage from the flash memory and never runs the program.  In each case it is trying to load the code from Flash into SRAM and run from SRAM. The code is small enough (including data) to fit in the SRAM.  Debugging and Signal Tap II traces of the Flash memory suggest that when running properly the Flash memory is read from address 00000 with data in order: 3A 70 01 00 74 00 C0 04 3A 48 01 98 04 F8 FF 9C  However, after pressing the reset button, the flash memory is read from address 00000 again, and the timing of the CE_n and OE_n signals is the same it reads back: 1F 00 C0 01 98 98 01 00 FF FF FF FF FF FF FF 02  If I power cycle the board it will read the contents properly again and run properly without needing another reset first. This implies that the Flash memory is not being overwritten. If I use the NiosII debugger I can read memory from address 00000 and I get back the incorrect version.  Any clues?

[Altera_Forum]

Ok, a co-developer has come up with a lot more information on this, but no definitive answer. The upshot is that after booting and copying to SRAM and running in SRAM, any further accesses to the Flash memory are corrupted. 

 If however you then try and 'write' to address 00000000 (without going through the actual write procedure, so the reset address doesn't get corrupted) then everything works normally. What is going on here? Is the CFI getting confused as to what state the flash memory is actually in?  If anyone can help it would be greatly appreciated.  Cheers, Simon

[Altera_Forum]

Do you have a hardware reset to the flash? 

 Jake

[Altera_Forum]

The hardware reset signal to the flash memory is kept high at all times. This is true both in this design which doesn't work and other designs on the same board that do work. 

 Cheers, Simon

[Altera_Forum]

The very first thing I would try is either a soft or hard reset to the flash. The flash most likely powers-up in read array mode. But truly you have no idea what state the flash is in if you perform a random reset. Issuing the write command puts the flash into a known state. Start with the reset and go from there. 

 Jake

[Altera_Forum]

Jake, 

Many thanks. I have implemented two things which seems to have cured this - at least in part. 1) as per your suggestion, the FPGA reset pin which also drives the CPU reset pin now drives the Flash reset pin as well and 2) after the FPGA comes out of reset it waits 2 seconds before releasing the CPU reset. This works now for power-on-reset and for pressing the reset button, but if the CPU issues its own reset it still needs to reset the Flash manually. Exactly why the Flash would not be in read mode after boot up is still a puzzle to me, but maybe it is to do with the latest 9.1 CFI driver?  Anyway, all working well enough now! Cheers, Simon

[Altera_Forum]

I'm glad you got it working. 2 seconds seems excessive but if it's not a problem for you then oh well. 

 Jake

[Altera_Forum]

I found the flash programmer of Nios II 9.1 IDE and Nios II 9.1 Software Build Tools for Eclipse both can not work normally.