Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Honored Contributor I
948 Views

Cache invalidation APIs and its usage in Altera Cyclone V SOC Linux

Hi all, 

 

We are conducting a feasibility study on our Altera Cyclone V SOC.  

We are having some streaming data receiving at FPGA at 300 Megabits per second. 

We have to transfer this data without any packet loss to a server machine over WiFi connection. 

UDP client application works on Altera SOC and server application works on an Ubuntu desktop machine. 

 

Initially we tried out a sample UDP_client and UDP_Server application which sends hardcoded buffer of data [from user space only. Not data read from FPGA via kernel space] to measure the maximum data rate over WiFi. 

We got the range of 250Mbps to 500Mbps. [Without tuning and tuning some network parameters as suggested in the link ["]https://opensourceforu.com/2016/10/n...e-monitoring/] (https://opensourceforu.com/2016/10/network-performance-monit

 

We are running Angstrom Linux supplied by Altera (Linux kernel version 4.9). 

 

We are using interrupt driven design with FPGA writing data to a ring buffer implemented in DDR. 

This ring buffer is mmapped to user space during application start.  

 

We are experiencing data miss which we later found that data is actually missed even between kernel space and user space. 

Hence we limited our analysis to client side by commenting out the send() function to server. 

 

On analysing the sequence numbers, we understood that some of the sequence numbers are stale data residing in the memory. 

This we have confirmed by doing a simple exercise. 

 

After reading each data packet including sequence number, we write the sequence number back to memory as zero. 

When we run this code, sequence number mismatch is not seen.  

 

We would like to know how can implement this in software by including any cache invalidation routines. 

We have tried out APIs like __cpuc_flush_kern_all(); and flush_cache_all(); before every time informing FPGA to write data to DDR. 

But these APIs do not work. 

 

Could you please help us with the cache invalidation APIs and the exact workflow in which cache invalidation APIs are to be used in Altera Linux SOC? 

 

Thank you, 

Lullaby
0 Kudos
1 Reply
Highlighted
Honored Contributor I
23 Views

Hi all, 

 

We are waiting for any help from you. We are almost blocked now. Not able to solve our issues with the APIs we found out.  

 

Just point out to us.. which are the cache invalidation APIs that could be used for Altera Cyclone V SOC running Linux? 

Or do we need to go for configuring ACP (just read in manual)? Which is effective?  

Could you please give some valuable thoughts on this? Any examples that we can refer for either case? 

 

Thank you, 

Lullaby
0 Kudos