Hi all,I'm want to test the PLL outputs for a nios system in a MAX10 fpga. I was told in another thread that I needed to add a clock bridge to simultaneously connect the output (c0 or c1) internally and externally. Instead of adding the clock bridge I decided to go really simple. I made a new project with just a clock source and the ALTPLL. I exported c0 and c1. Then, in the pin planner, I connected them to a couple of pins (I think it was PIN_A2 and PIN_A3). I programmed the sof file, connected the scope to the pins and nothing showed up. So I tried to program the pof file (CFM0). Still I see nothing in the scope. Am I doing this right in the sense that it is possible? or do I still need the clock bridge to connect c0 and c1 to physical pins? BTW qsys did complaint (warning) about a slave connection missing. Thanks
Yes, it is perfectly valid to connect both c0 & c1 to device pins. If you're struggling I suggest you post (the source code for) your project and we can have a look. Zip up the .qsf, .qpf, .qsys and any verilog/vhdl files you're using.Cheers, Alex
It worked!!!!! I tried again and this time I unchecked all boxes for extra pins and didn't export them. Qsys gave me warnings about it but I ignored them. I set the c0 and c1 outputs really low to start (5kHz) and gradually tried higher and higher. The square wave doesn't look like a squarewave at 50MHz but at least it is there. Now I can move on to using it with an SDRAM. I'm pretty sure I'll be posting some questions when/if I get stuck. Thank you!.
Glad you're up and running.Your 50MHz 'square' wave is likely not to look like a square wave due to limitations of your oscilloscope. What is the bandwidth of your oscilloscope? If it's only 100MHz or so then your 50MHz wave square wave shape is likely to be rather sinusoidal. If your scope is a little better (500MHz+), and the waveform still looks a little rubbish, then you are probably loading the clock too heavily. I trust your 5kHz square wave looks as you'd expect... Cheers, Alex