Can Nios be synthesized by Synplify or Amplify

Altera_Forum · ‎09-10-2004

If yes, how?

Thanks

Altera_Forum · ‎09-10-2004

The SOPC builder outputs vhdl/verilog files and memory initialization files (mif/hex) so I don't see why not (never done it, I just use Quartus for altera FPGAs).

But to use the SOPC builder you have to have Quartus installed.

So as long as you can get the block it generates into those programs you're fine (never used Amplify before, and everything I did in Synplify was VHDL (using that other FPGA company hehe) so I can't be 100% sure (but if it doesn't handle block stuff you could do some vhdl to map the I/O anyway))

G-luck

Altera_Forum · ‎09-10-2004

Modelsim is what we claim support for, but our Verilog and VHDL are industry standard, so you should be able to put the .v or .vhd files into any simulator and make it simulate. Otherwise, since Sopc Builder gies you the v or vhd you should be able to go to most other applications for whatever...

One thing I remember is that some applications have problems with long signal names. That would be a problem with Sopc Buidler generated files, they're long.

Altera_Forum · ‎09-13-2004

Hi,

one may use Synplify or Amplify for compiling Nios. But I'll strongly recommend to compile Nios using Quartus.

One will acheive better results both in timing and area for the Nios processor. I guess, the circuit description is optimized for the Quartus synthesis tool.

Regards