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Altera_Forum
Honored Contributor I
969 Views

Can not understand TIMEQUEST cookbook tSU, tH, and tCO Constraints need help

This is from "Quartus Prime TimeQuest Timing Analyzer Cookbook 2016.2.25" page 14. 

 

http://www.alteraforum.com/forum/attachment.php?attachmentid=12510&stc=1  

# Specify the clock period set period 10.000# Specify the required tSU set tSU 1.250# Specify the required tH set tH 0.750# Specify the required tCO set tCO 0.4# create a clock 10ns create_clock -period $period -name clk # create the associated virtual input clock create_clock -period $period -name virt_clk set_input_delay -clock virt_clk -max }] set_input_delay -clock virt_clk -min $tH }] set_output_delay -clock virt_clk -max }] set_output_delay -clock virt_clk -min }]  

 

I think if change the -max/min into -late/early probably will become more understandable. 

I can understand the set_input_delay very clearly, but the set_output_delay make no sense to me. 

 

Here is the questions:# 1 the red marked tH never be used here, why?# 2 the red marked tco_min never be defined, why?# 3 why the set_output_delay -min is a negative value, what does this mean?
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3 Replies
Altera_Forum
Honored Contributor I
36 Views

 

--- Quote Start ---  

 

 

 

 

I think if change the -max/min into -late/early probably will become more understandable. 

I can understand the set_input_delay very clearly, but the set_output_delay make no sense to me. 

 

Here is the questions:# 1 the red marked tH never be used here, why?# 2 the red marked tco_min never be defined, why?# 3 why the set_output_delay -min is a negative value, what does this mean? 

--- Quote End ---  

 

 

You got a point. There are several ways delay figures are derived but remember no matter how you got them the tool only sees these figures and doesn't care about how you derived them. 

 

Firstly, tH is used in set_input_delay above. 

secondly, tCO_min is undeclared by mistake from editor. 

 

using early/late margin(arrival) is excellent but TQ wants delay values. 

 

The classic way is to use figures of tCO(min&max) of external device for input delay values and use tSU/-tH of output device for output values. 

 

However, some vendors do not give such figures. For example they give values of required tSU/tH at fpga for their inputs to fpga or values of required tCO from fpga to their device. This creates a mirror concept, then you have to work out how to convert them to delay values. The best way is to think through early/late margin. 

 

For input, delay values correspond directly to early/late arrival relative to launch edge: 

early margin = min delay = min tCO = tH i.e. min delay = tH (margin should avoid previous latch edge) 

late margin =max delay = max tCO = clock period - tSU, i.e. max delay = clock period - tSU (margin should avoid next latch edge) 

 

for output, delays correspond as follows (notice it is not symmetrical with inputs value approach and they are relative to latch edge): 

early arrival = -min delay, hence delay = - early arrival = - min tCO (explained below) 

late arrival = clock period - max delay, hence delay = clock period - max tCO (explained below) 

 

The negative tH is a consensus issue and is due to delay values being relative to latch edge(outside fpga), early margin is the one after latch edge and late margin is the one before latch edge while naturally early/late margins are relative to launch edge inside fpga and directly equal min/max tCO. very confusing and you should have never needed to use such approach but are imposed by some vendors. 

Finally I think the valid output window is not right in above diagram
Altera_Forum
Honored Contributor I
36 Views

Thank you very much kaz, that's an excellent explanation.  

 

I have a another question, would you help me? I'm kind of stuck here for days. 

 

This is reports generated by TIMEQUEST "Report Datasheet". 

 

Here is the question: 

1. How can I calculate tSU, tH, and tCO from rise & fall in this report?  

2. What does this rise and fall mean or represent for? 

 

Setup Times 

Data Port Clock Port Rise Fall Clock Edge Clock Reference SDRAM_DQ CLKIN_50M 3.776 3.951 Rise u1|altpll_component|auto_generated|pll1|clk SDRAM_DQ CLKIN_50M 3.754 3.929 Rise u1|altpll_component|auto_generated|pll1|clk SDRAM_DQ CLKIN_50M 3.766 3.941 Rise u1|altpll_component|auto_generated|pll1|clk SDRAM_DQ CLKIN_50M 3.766 3.941 Rise u1|altpll_component|auto_generated|pll1|clk SDRAM_DQ CLKIN_50M 3.740 3.915 Rise u1|altpll_component|auto_generated|pll1|clk  

 

Hold Times 

Data Port Clock Port Rise Fall Clock Edge Clock Reference SDRAM_DQ CLKIN_50M -3.122 -3.297 Rise u1|altpll_component|auto_generated|pll1|clk SDRAM_DQ CLKIN_50M -3.153 -3.328 Rise u1|altpll_component|auto_generated|pll1|clk SDRAM_DQ CLKIN_50M -3.165 -3.340 Rise u1|altpll_component|auto_generated|pll1|clk SDRAM_DQ CLKIN_50M -3.165 -3.340 Rise u1|altpll_component|auto_generated|pll1|clk SDRAM_DQ CLKIN_50M -3.139 -3.314 Rise u1|altpll_component|auto_generated|pll1|clk  

 

Clock to Output Times 

Data Port Clock Port Rise Fall Clock Edge Clock Reference CORE_CLK CLKIN_50M 0.900 Rise u1|altpll_component|auto_generated|pll1|clk SDRAM_A CLKIN_50M 0.823 0.796 Rise u1|altpll_component|auto_generated|pll1|clk SDRAM_A CLKIN_50M 0.818 0.791 Rise u1|altpll_component|auto_generated|pll1|clk SDRAM_A CLKIN_50M 0.818 0.791 Rise u1|altpll_component|auto_generated|pll1|clk SDRAM_A CLKIN_50M 0.823 0.796 Rise u1|altpll_component|auto_generated|pll1|clk SDRAM_A CLKIN_50M 0.813 0.786 Rise u1|altpll_component|auto_generated|pll1|clk
Altera_Forum
Honored Contributor I
36 Views

seems to me you are gong opposite the rules. 

You get your delays from device data sheets then apply it and see what TQ achieves. 

In TQ go to report io timing or datasheet section and it will give tSU,tH and tCO achieved
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