I've made a sopc system in which the niosii cpu's reset vector is in cfi_flash and exception vector is in sdram.I can run and debug my program in eclipse very well, but when I use flash programmer download the .elf file into cfi_flash, the nios won't boot when power up. If I change the exception vector of niosii into onchip memory and change every section in the Linker script to onchip memory, nios can boot. I guess the problem is that when power up, data can't be loaded correctly from flash into sdram, but as I can run program in sdram using eclipse, the sdram core seems no problem.
The problem is solved, I'm using sdram K4S641632k. I know that the problem is very likely related to the byte enable signal.So I double checked the ldqm and udqm signal of sdram, it's connected to the fpga correctly. I was shocked ten minutes ago when the pcb designer tell me he had switched the high/low byte signals of sdram for easy routing.