Hi,I've got a design including a Nios 2 working on my De0 nano board. I read the tutorials for setting up a Nios 2 in Qsys, I just added some more pio for my signals. I'm also using the SDRAM, so I am using the clocks module from the university program, which might make a difference to my question. The design works fine at the moment, but I would like to run the processor a little bit faster. I assumed I could use a PLL to generate my faster clock, pass this to the Nios processor when I instantiate it, and change the input clock frequency from 50MHz to whatever my new clock is in my Qsys design. However, after I've done this I get the 'unable to download ELF' message in Eclipse. I regenerated the BSP, are there any other steps I missed out? Or is it not possible to clock the processor faster in this way? Thanks for your help. Bert
I didn't mention that step because I thought it was too obvious, but yes, I did reprogram the FPGA! Does it sound like it should have worked otherwise? Could it be that the logic that the PIO connects to is still running at 50MHz while the processor is running faster?
I must say, that I don't like how your reset signals are connected together. clk_reset goes to reset_n. Is it possible, that your Nios II does not leave reset state?
I'll look through the tutorials again to see if I've got that wired right. It must be leaving reset though, because it works fine when I am using a clock of 50MHz, unless that would change for some reason with a faster clock.
Hi Linas,The PLL is a mega function in my verilog code, that is working correctly because I can see it on an output pin. I've actually managed to resolve the issue by starting a new project in eclipse and pasting my existing code in. It's almost as if the generate BSP function doesn't do what it's supposed to (or what I think it does) after changing the hardware. Thanks for all your help anyway!