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Altera_Forum
Honored Contributor I
1,404 Views

Comments on Embedded Operating Systems for the Cyclone V

Hello, I would like to hear some comments about the following Embedded Operating Systems. I'm curious which one is the best Real-Time OS and which ones are the easiest to us.  

 

Linux 3.7 

VxWorks 6.9.2 

uC/OS-11, uC/OS-III 

OSE 5.5.3 

ThreadX 5.5.3 

Wind river Linux 5 

QNX/Neutrino 6.5.3 

Android 

Integrity 

Windows Embedded 7 

 

Thanks, 

joe
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4 Replies
Altera_Forum
Honored Contributor I
39 Views

Arguably this is the wrong question to start with ... 

 

The correct way to analyze your system is; 

 

1. What are my real-time requirements? 

2. Will/Can those real-time requirements be met by a hardware or software solution? 

3. Who will be maintaining this system? 

4. Do I need to use an FPGA? 

 

The answer to (4) may be a result of (1+2), i.e., the real-time requirements can be met in hardware by an FPGA. At that point, your operating system becomes non-real-time control software, and support of this software is (in my opinion) simpler via Linux. 

 

If your analysis indicates that a microcontroller can meet your real-time requirements, then uCOS-II/III is a nice solution (its very well documented). 

 

The Cyclone SoC devices are very complex beasts. When it comes to software support, its critical (to your sanity) to select an operating system where the majority of the work has already been done for you, and the maintenance on that software will continue without you. That means you should try to run U-Boot and Linux. The source code for U-Boot and Linux is currently being mainlined, and is actively supported by major players like Denx (the maintainers of U-Boot) and Altera's SoC developers (via RocketBoards.org). 

 

Cheers, 

Dave
Altera_Forum
Honored Contributor I
39 Views

Dave, 

 

HI, in my application I would have a process that has real-time priority. The processor would run in a loop that executes every 300usec. During that time it would receive data from the FPGA side, process the data and then DMA the data to a PCIe channel. The DMA should occur at or very near the same time for every 300usec loop, such as at 150usec within the 300usec loop. Can any RTOS run with this types of constraints? 

 

Thanks, 

joe
Altera_Forum
Honored Contributor I
39 Views

Dave, 

 

HI, do you know if the following will run on a Cyclone V? 

 

http://linux.web.cern.ch/linux/mrg/ 

 

We are running this on our computers and I was wondering if it can run on a FPGA. This is a port of the MRG kernel from RedHat. It's designed for the Scientific Linux distribution, but it works fine with our CentOS 6 systems. If would be nice if I as able to use the same OS. 

 

Thanks, 

joe
Altera_Forum
Honored Contributor I
39 Views

Hi Joe, 

 

--- Quote Start ---  

 

The processor would run in a loop that executes every 300usec. During that time it would receive data from the FPGA side, process the data and then DMA the data to a PCIe channel. The DMA should occur at or very near the same time for every 300usec loop, such as at 150usec within the 300usec loop. Can any RTOS run with this types of constraints? 

 

--- Quote End ---  

 

Sure, an RTOS can run with that constraint. However, have you determined that the required processing can be completed in the time required? It does not matter if your RTOS can schedule tasks in real-time, if your processor cannot perform the processing. 

 

It would be easier to recommend a solution if you could provide information on what the processing is. If that processing can be implemented in an FPGA, or can be accelerated by an FPGA, then your software would not need to be real-time. 

 

Cheers, 

Dave
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