Re: Compile Failed with recursively call by uclinux project

Altera_Forum · ‎09-24-2014

Hi,

I got some problem of porting uclinux on de2-115 board.

Top level entity name is uclinux.v

i tried to compiling project, and have error.

here is code,

module uclinux(			CLOCK_50,
			UART_RXD,
			UART_TXD,
			DRAM_WE_N,
			DRAM_RAS_N,
			DRAM_CS_N,
			DRAM_CLK,
			DRAM_CKE,
			DRAM_CAS_N,
			DRAM_DQM,
			DRAM_DQ,
			DRAM_BA,
			DRAM_ADDR
);
input		CLOCK_50;
input	 	UART_RXD;
output	UART_TXD;
output				DRAM_CAS_N;
output				DRAM_CS_N;
output				DRAM_CKE;
output				DRAM_WE_N;
output		DRAM_ADDR;
output				DRAM_RAS_N;
output			DRAM_DQM;
output		DRAM_DQ;
output			DRAM_BA;
output				DRAM_CLK;
wire	sys_clk;
uclinux uc (
		.clk_clk			(sys_clk),
		.reset_reset_n	(1),
		.sdram_wire_addr		(DRAM_ADDR),
		.sdram_wire_ba			(DRAM_BA),
		.sdram_wire_cas_n		(DRAM_CAS_N),
		.sdram_wire_cke		(DRAM_CKE),
		.sdram_wire_cs_n		(DRAM_CS_N),
		.sdram_wire_dq			(DRAM_DQ),
		.sdram_wire_dqm		(DRAM_DQM),
		.sdram_wire_ras_n		(DRAM_RAS_N),
		.sdram_wire_we_n		(DRAM_WE_N),
		.uart_external_connection_rxd			(UART_RXD),
		.uart_external_connection_txd			(UART_TXD)
);
pllnios n0 (
	.inclk0(CLOCK_50),
	.c0(sys_clk),
	.c1(DRAM_CLK)
);
endmodule

and with this error message,


Info (12127): Elaborating entity "uclinux" for the top level hierarchy
Info (12128): Elaborating entity "uclinux" for hierarchy "uclinux:u0"
Info (12128): Elaborating entity "uclinux" for hierarchy "uclinux:u0|uclinux:u0"
Info (12128): Elaborating entity "uclinux" for hierarchy "uclinux:u0|uclinux:u0|uclinux:u0"
...
Info (12128): Elaborating entity "uclinux" for hierarchy "uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0|uclinux:u0"
Error (12051): Project too complex: hierarchy path is too long
     Error (12052): Entity "uclinux" is instantiated by entity "uclinux"

why cause recursively call to 'uclinux' module in this project?

Altera_Forum · ‎09-24-2014

You are recusivelly instantiating module inside a module because the top module has the same name as QSys module. I would suggest you change one of them.

Altera_Forum · ‎09-24-2014

Thanks to You're suggestion, But I think this problem caused by 'uclinux:u0 ' macro function.

I already tried change from 'uclinux u0' to 'uclinux uc'. And then, I got same error message again.

So, What could i do solve this problem?

Altera_Forum · ‎09-24-2014

If the top module is named uclinux there should be no modules named uclinux in it. I would suggest you either change qsys name or top level name.

Also, this is a Verilog question and it should be in different forum.

Altera_Forum · ‎09-24-2014

Oh, I'm really appriciate your help.

I changed macro name from 'uclinux' to 'niosqsys', and successfully compile it.

Thank you janco.