Component Editor Error

[Altera_Forum]

When I try to add a simple file like the below in Component Editor it fails. 

????????????? It happens for all file, more comleks than this eksample to.  <div class='quotetop'>QUOTE </div>  --- Quote Start ---  Error: command "quartus_map --generate_hdl_interface=E:/bjornar/workspace/altera/spectrometer/ce_temp_directory/demo.vhd ce_temp_directory/ce_temp_quartus_project" returned 3 Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 0 warnings     Error: Processing ended: Wed Feb 08 21:25:04 2006     Error: Elapsed time: 00:00:03 Error: E:/bjornar/workspace/altera/spectrometer/ce_temp_directory/demo.vhd.xml does not exist[/b]  --- Quote End ---    library ieee, std; use ieee.std_logic_1164.all, ieee.numeric_std.all, std.textio.all; entity demo is     port     (  -- Avalon interface  clock    : in    std_logic;  reset_n    : in    std_logic;    chipselect      : in    std_logic;  address    : in  std_logic_vector(31 downto 0);    write    : in    std_logic;  write_data      : in    std_logic_vector(31 downto 0);    read    : in  std_logic;  read_data      : out  std_logic_vector(31 downto 0);    irq        : out    std_logic;       ); end demo; architecture behavior of demo is begin end architecture;

[Altera_Forum]

--- Quote Start ---  originally posted by doofus64@Feb 8 2006, 01:31 PM when i try to add a simple file like the below in component editor it fails. ????????????? it happens for all file, more comleks than this eksample to.  <div class='quotetop'>quote   --- quote end ---    --- quote start ---  error: command "quartus_map --generate_hdl_interface=e:/bjornar/workspace/altera/spectrometer/ce_temp_directory/demo.vhd ce_temp_directory/ce_temp_quartus_project" returned 3 error: quartus ii analysis & synthesis was unsuccessful. 1 error, 0 warnings     error: processing ended: wed feb 08 21:25:04 2006     error: elapsed time: 00:00:03 error: e:/bjornar/workspace/altera/spectrometer/ce_temp_directory/demo.vhd.xml does not exist  --- Quote End ---     <div align='right'><{post_snapback}> (index.php?act=findpost&pid=12643)</div> [/b]  --- Quote End ---    doofus64,  Did you try to compile the VHDL file first in Quartus II to see if it will pass compilation before importing the VHDL file into the Component Editor?   Your VHDL or Verilog design must pass Quartus compilation first before you start to import the HDL file as a component into SOPC builder. If you noticed from the log output "quartus_map.exe" is the start of analysis and mapping of Quartus II Synthsis (if you use Quartus II scripting) and you have no logic in your design to map. I would expect the importing of incomplete HDL code in component editor to error out very early in the process.  Regards, -ATJ

[Altera_Forum]

The project I have, compile fine in quartus. And there is generatet logic out. I can se the logic in "Chip Editor". Do any have an example project to try. I know there are I example in the tutorial for the soap builder, but I can&#39;t find it.

[Altera_Forum]

--- Quote Start ---  originally posted by doofus64@Feb 8 2006, 10:31 PM <div class='quotetop'>quote   --- quote end ---    --- quote start ---  error: command "quartus_map --generate_hdl_interface=e:/bjornar/workspace/altera/spectrometer/ce_temp_directory/demo.vhd ce_temp_directory/ce_temp_quartus_project" returned 3 error: quartus ii analysis & synthesis was unsuccessful. 1 error, 0 warnings  --- Quote End ---      irq        : out    std_logic;     ); end demo; <div align='right'><{post_snapback}> (index.php?act=findpost&pid=12643)</div> [/b]  --- Quote End ---    Hi,  I got the similar problem with Quartus II 5.1 i.e. the Component Editor failed to import the VHDL code but didn&#39;t give details about the error.  After upgrading to Quartus II 5.1 SP1 the errors from quartus_map program are correctly shown in the error dialog.  And by the way, my guess is that the semicolon at the end of that "irq" port definition line is the problem, you might want to remove that last semicolon and see what happens ...  Regards, Jari

[Altera_Forum]

--- Quote Start ---  originally posted by doofus64@Feb 9 2006, 12:01 AM the project i have, compile fine in quartus. and there is generatet logic out. i can se the logic in "chip editor". do any have an example project to try. i know there are i example in the tutorial for the soap builder, but i can&#39;t find it. <div align='right'><{post_snapback}> (index.php?act=findpost&pid=12650)  --- quote end ---    --- Quote End ---    doofus64,  The example and tutorial for the component editor can be found on the Altera literature web page.  http://www.altera.com/literature/quartus2/lit-qts-sopc.jsp (http://www.altera.com/literature/quartus2/lit-qts-sopc.jsp)  Chapter 5 covers the features of the component editor. http://www.altera.com/literature/hb/qts/qts_qii54005.pdf (http://www.altera.com/literature/hb/qts/qts_qii54005.pdf)  If you look at chapter 9 it has the tutorial flow for building a pulse-width modulator. http://www.altera.com/literature/hb/qts/qts_qii54007.pdf (http://www.altera.com/literature/hb/qts/qts_qii54007.pdf)  The design files for the tutorial can be found in the link below chapter 9. http://www.altera.com/literature/hb/qts/pwm_source.zip (http://www.altera.com/literature/hb/qts/pwm_source.zip)  Regards, -ATJ