Nios® II Embedded Design Suite (EDS)
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Configuration of on-chip memory width for dual port access

BeB
Beginner
304 Views

Hello,

 

I am using Quartus 19.1. I would like to use a dual-port RAM to pass data from the fabric to the Nios soft processor.

 

It is my understanding that the Nios port width must be set to 32 bits, but I would like to write 64 bits at a time from the fabric.

 

However, the option 'enable different port width for dual port access' is always greyed out, and therefore now available. I have attached a screenshot.

 

I would like to not have to write 2x 32 bits from the fabric.

 

How do I enable different port width?

 

Thank you,

BeB

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2 Replies
EricMunYew_C_Intel
Moderator
288 Views

Nios II supports 32 bit data width. Therefore you can't write 64 bit data from the FPGA fabric.

It will take two cycles to write 64 bit data.


EricMunYew_C_Intel
Moderator
277 Views

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


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