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Altera_Forum
Honored Contributor I
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Configuring Altera FPGAs

I am currently working on a project using a cyclone ii device and I am not sure I understood the Configuration Cycle Waveform as described in ALTERAs config_handbook.pdf correctly : (Figure 1-1) 

 

When the system powers up, the Low-to-High transition of CONF_DONE indicates the end of the configuration phase. 

Then registers and I/O-pins are initialized before the devices enters the User-Mode, indicated by a Low-to-High transition of INIT_DONE. 

 

My question is : 

 

In VERILOG-1995 registers can be initialized using an INITIAL block. 

My code consists of a large number of modules each of them using an INITIAL block. 

 

Are all registers affected by that command initialized during that initialization phase as mentioned above (between CONF_DONE transition and INIT_DONE transition) ? 

 

I am using QUARTUS 9.1SP2 software. 

 

Thanks.
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Altera_Forum
Honored Contributor I
39 Views

Hi, 

I think all registers must be initialized to either "0" or "1" before the device enters user mode. In case there is no initialization within the code (and the option "Power-Up don't care" in "More analysis&synthesis settings" is "On"), the QuartusII compiler can decide to initialize to either "1" or "0" to optimize device usage... 

(Similar to initialization in Code there is an "Power-Up Level" option in the assignment editor...) 

 

Regards
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