Re: Configuring FPGA through EPCS (EEPROM) INCLUDING Nios II program?

Altera_Forum · ‎11-26-2013

Hello people!

I have made numerous VHDL applications where I configure the FPGA on boot via the EPCS (EEPROM) chip. So until now I know how to create a .jic file and save it to the EEPROM so that the program stays while power is off and be again reconfigured when powered on again.

Now I would like to create a small monitoring apllication in Nios II to communicate with the rest of the VHDL system through some parallel ports. My problem is that until now I have only seen in tutorials how to load the Nios II program on-the-fly using ALTERA Monitor Program.

Is there any possibility that I incorporate the Nios II program into the .jic file so that when I power on the board the Nios II program will get loaded in the on-chip RAM while the rest of the FPGA configuration is done?

Thanks

Altera_Forum · ‎11-26-2013

Sure you can!

First of all you need to build a hex file including both fpga configuration and nios firmware.

From a nios shell window you need to send these commands:

sof2flash --epcs --input=fpga_project.sof --output=fpga_project.flash

elf2flash --epcs --after=fpga_project.flash --input=nios_firmware.elf --output=nios_firmware.flash

cat fpga_project.flash nios_firmware.flash > hw_sw.flash

nios2-elf-objcopy -I srec -O ihex hw_sw.flash hw_sw.hex

Then, in Quartus select File->Convert programming Files

Select JTAG INdirect Configuration File (.jic) at "Programming file type".

Select your EPCS configuration device model and write the desired output filename .jic.

In the bottom box select Flash Loader -> Add Device, and then select your fpga model.

If any sof line is already there, delete it; then select Add Hex data with the previously generated file.

Press "Generate".

I recommend to save the configuration (.cof) file, so you avoid to setup everything again when you need to generate a new version. You could also automate the shell commands in the beginning with a script file.

Altera_Forum · ‎11-26-2013

Hey thanks!!

So if i understand correct I need to compile my hardware system + Nios as usual, creating a .sof file.

Then create an .elf file by building my software in Eclipse SBT (just started learning the Eclipse SBT by the way).

And then run the commands that you wrote me so that I create one hex file with all the configuration inside. (Can I have access to the Nios shell tools inside the Eclipse SBT?)

Another question is whether I can have this hex file created automatically in the Eclipse SBT. So that after a successful build, I just give the .sof file location and the hex file is created automatically.

Is that possible?

Regards

Altera_Forum · ‎11-26-2013

That is the EPCS flash loader sequence.

What you should be able to do is extrace the sections from the elf file and use each one to generate an initialisation file for the relevant memory block.

I generate an elf file that includes two code and two data sections that need initialising (and some sections that don't).

$ objdump -h mtp2.elf
mtp2.elf:     file format elf32-little
Sections:
Idx Name          Size      VMA       LMA       File off  Algn
  0 prot_code     00002078  00008000  00008000  000000f4  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, CODE
  1 hdlc_code     00000a50  0000c000  0000c000  0000216c  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, CODE
  2 shared_data   00002000  00014000  00014000  00002bbc  2**2
                  ALLOC
  3 prot_data     00002b3c  00018000  00018000  00002bbc  2**4
                  CONTENTS, ALLOC, LOAD, DATA
  4 hdlc_data     00002e08  0001c000  0001c000  000056f8  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  5 sdram         00a38000  01000000  01000000  00008500  2**15
                  ALLOC
  6 .comment      000001ce  00000000  00000000  00008500  2**0
                  CONTENTS, READONLY
  7 unwanted      00000000  0001c000  0001c000  000056f8  2**0
                  CONTENTS, ALLOC, LOAD, CODE

I actually use objcopy to convert them into ppc object files, but I generate raw binary files on the way.

Makefile fragment below:

# Convert sections from nios2 program into readonly data areas that can
#  be linked into the loading program.
#  We must cd to $(OBJDIR) to avoid getting the directory path prepended
#  to the symbol names objcopy adds to the created file.
#  Flags for objcopy to generate the correct section type from raw data
SECT = $(notdir $(@:.o=))
FL_GEN = --rename-section .data=.rodata.$(SECT),alloc,load,readonly,data,contents
OBJ_FLAGS = -O elf32-powerpc -B powerpc
$(NIOS_SECT_OBJS): $(OBJ_DIR)/mtp2.elf
        @ echo '### create $@'
        $(NIOS_OBJCOPY) -O binary -j $(SECT) $^ $(@:.o=.x)
        cd $(OBJ_DIR) && { 
              $(OBJCOPY) -I binary $(OBJ_FLAGS) $$FL_GEN $(SECT:=.x) $(SECT:=.o); 
        }
        rm -f $(@:.o=.x)

I'm not sure what format you need the M9K initialisation data in, you might not need two objcopy call, and you'll certainly need different values for OBJ_FLAGS for the second one.

Altera_Forum · ‎11-26-2013

If you use the EPCS boot code you'll also need the instruction cache (you can't use tightly coupled memory for it).

If nothing else needs access to your code/data space then tightly couple it as both code and data memory.

There is no point at all using either cache for on-chip memory.

(It really ought to be possible to tightly couple both the JTAG code and the EPCS boot code.)

My example is a two cpu system, loaded over PCIe. It is real code and those are the correct sizes.

The original plan was to tightly couple the 'shared_data' to both cpu, but it is useful to be able to read it over PCIe for diagnostics so one of the cpus takes the slight performance penatly of Avalon transfers.

Altera_Forum · ‎11-26-2013

You seem to be making pretty much advanced applications. I tried to start from the simple steps first. Meaning, I am trying to incorporate a higher-level control-supervision to my FPGA projects which include VHDL code for PWM, ADC control and some other low level functionality. So what I would like is a very small tutorial on how to incorporate a small software together with Nios to my VHDL projects (available at boot - so EEPROM saved).

In general the Nios platform in my application will just accept and deliver some parallel ports to the rest of the VHDL system and enable/disable VHDL functionality, provide some real time debugging through UART, maybe implement some 7-segment display, LCD, and very simple USB or Ethernet communication.

Apart from all these I would like to have some ideas on memory strategy like where to store the program, the data, the general FPGA configuration bitstream, etc.

Also maybe it would be better to save the main program in an external EEPROM and configure a small part of the on-chip RAM with a small software to go and copy the main program from the External EEPROM to another External SDRAM and run the main program from there (faster?).

Just ideas......

My main problem now is to incorporate a basic NiosII (e version) plus a small program, to the whole FPGA configuration file with the rest of my VHDL code, save it to an external EEPROM and configure the whole thing at power-on.

THANKS IN ADVANCE!

Altera_Forum · ‎11-26-2013

FYI

I have both DE0-Nano and DE2-115.

What could I do with these regarding the aforementioned message?

Altera_Forum · ‎06-11-2015

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