Configuring fpga in jtag and as mode

[Altera_Forum]

Hi, 

Iam new to altera fpga, iam using cyclone ii fpga , in datasheets it is given that, fpga can be configured in four modes(jtag,as and ps).but in evaluation schematics it is given with the on board usb blaster circuit which i don't want to implement.  if i want to implement configuration of fpga with out on board usb blaster in two modes (jtag, as),then how to give the conections between fpga, serial eeprom and jtag.

[Altera_Forum]

You don't say why you want your board to support AS and JTAG. 

 If it's so that it will normally be configured by AS, but JTAG is available for prototyping and debugging then you should connect the jtag pins on the device to a JTAG header, and you should connect the AS pins on the device to the serial eeprom.

[Altera_Forum]

You find respective configuration schematics in the FPGA device handbooks. My suggestion is the scheme "Programming Serial Configuration Devices In-System Using the JTAG Interface" which uses only a JTAG header and programs the AS memory through JTAG. Alternatively, you have the "Combining JTAG and AS Configuration Schemes" with separate AS and JTAG headers.

[Altera_Forum]

--- Quote Start ---  You find respective configuration schematics in the FPGA device handbooks. My suggestion is the scheme "Programming Serial Configuration Devices In-System Using the JTAG Interface" which uses only a JTAG header and programs the AS memory through JTAG. Alternatively, you have the "Combining JTAG and AS Configuration Schemes" with separate AS and JTAG headers.  --- Quote End ---     thanks for u r response,    i have one question about run/prog switch used in evaluation schematics, is this switch is necessary for designs with out on board usb blaster circuit.

[Altera_Forum]

--- Quote Start ---   i have one question about run/prog switch used in evaluation schematics, is this switch is necessary for designs with out on board usb blaster circuit.  --- Quote End ---    The USB-Blaster schematic you see in the evaluation board you have (which I assume is the DE2) is a non-standard implementation of the USB-Blaster logic by Terasic. The RUN/PROG switch selects between the USB-Blaster operating in JTAG mode or AS mode, without having to move the USB-Blaster between 10-pin headers (which you cannot on this board, since the USB-Blaster is built-in).  The USB-Blaster CPLD logic is not open. You have to contact Altera for access, and I doubt that it supports this dual-mode feature.  For your custom board design, simply include the 10-pin JTAG header. You can program SPI flash devices like the EPCS configuration flash via JTAG indirect mode, so you do not need the AS header.  Cheers, Dave

[Altera_Forum]

--- Quote Start ---  The USB-Blaster schematic you see in the evaluation board you have (which I assume is the DE2) is a non-standard implementation of the USB-Blaster logic by Terasic. The RUN/PROG switch selects between the USB-Blaster operating in JTAG mode or AS mode, without having to move the USB-Blaster between 10-pin headers (which you cannot on this board, since the USB-Blaster is built-in).  The USB-Blaster CPLD logic is not open. You have to contact Altera for access, and I doubt that it supports this dual-mode feature.  For your custom board design, simply include the 10-pin JTAG header. You can program SPI flash devices like the EPCS configuration flash via JTAG indirect mode, so you do not need the AS header.  Cheers, Dave  --- Quote End ---        thank u for u r support.