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Honored Contributor I
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Create a timer

hello to everybody

i'm writing a custom logic , exactly a timer delayed 

In sopc builder i add my component , read ports , generate without problems.

After that in quartus II update my system , assign pins , compilation successfull ect .

In Nios II ide i choose my system , build project and seen in system.h my system 

and also my component added .I write macro and define my registers to write and read my timer delayed .

In the control register i set the first bit when i need to start my timer , and 

i read in status register the first bit to know when my timer expired .

Up to now everythings are ok but it's possible that in vhdl file where i describe my timer , something run no good .

I post my code vhdl 

 

 

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

USE ieee.numeric_std.ALL;

 

entity Timer_Ton is

port ( 

clk : in std_logic; -- avalon bus signal

reset : in std_logic; -- avalon bus signal

address : in std_logic_vector(1 downto 0); -- avalon bus signal 

writedata : in std_logic_vector(31 downto 0); -- avalon bus signal 

readdata : out std_logic_vector(31 downto 0); -- avalon bus signal 

chipselect : in std_logic; -- avalon bus signal 

write : in std_logic; -- avalon bus signal 

read : in std_logic; -- avalon bus signal 

waitrequest : out std_logic -- avalon bus signal 

 

); 

end;

 

 

architecture a of Timer_Ton is

 

signal busy : std_logic;

signal start: std_logic;

signal timer_done:std_logic;

signal mem: std_logic;

signal mem2: std_logic;

signal ok_count_timer:std_logic;

signal reg0w : std_logic_vector(31 downto 0); -- control register

signal reg0r : std_logic_vector(31 downto 0); -- status register

signal reg1w : std_logic_vector(31 downto 0); -- preset register

signal ms_counter:unsigned(31 downto 0);

signal preset:integer range 0 to 10800000;

signal counter_clock : unsigned(31 downto 0); 

begin

 

process(clk,reset)

begin

if(reset='1&#39 then

busy<=&#39;0&#39;;

waitrequest<=&#39;1&#39;;

readdata <= (others =>&#39;0&#39;

reg0w<=(others =>&#39;0&#39;

reg0r<=(others =>&#39;0&#39;

reg1w<=(others =>&#39;0&#39;

 

 

else if(rising_edge(clk)) then

if(chipselect=&#39;1&#39; and busy=&#39;0&#39 then 

busy<=&#39;1&#39;;

case address is

 

-- CONTROL REGISTER ADDRESS=0x00

when "00" => 

if(write=&#39;1&#39 then

reg0w <= writedata;

else if(read=&#39;1&#39 then

readdata <= reg0r;

end if; 

end if; 

waitrequest <=&#39;0&#39;; 

 

-- CONTROL REGISTER ADDRESS=0x01

when "01" => 

if(write=&#39;1&#39 then

reg1w <= writedata;

else if(read=&#39;1&#39 then

readdata <= reg1w;

end if; 

end if; 

waitrequest <=&#39;0&#39;; 

when "10" => 

if(write=&#39;1&#39 then

--reg2w <= writedata;

else 

if(read=&#39;1&#39 then

--readdata <= reg2w;

end if; 

end if; 

waitrequest <=&#39;0&#39;; 

when "11" => 

if(read=&#39;1&#39 then

-- readdata <= reg3r;

end if; 

waitrequest <=&#39;0&#39;; 

when others => null; 

end case;

end if; -- STB

 

if(chipselect=&#39;0&#39 then 

busy<=&#39;0&#39;;

waitrequest<=&#39;1&#39;;

end if; 

 

 

end if; -- CLK

end if; -- RST_i 

 

start<=reg0w(0);

reg0r(0)<=timer_done; 

 

end process; 

 

 

 

 

clockrocess(clk,start) 

 

begin

if(start=&#39;0&#39 then

ms_counter<= "00000000000000000000000000000000";

counter_clock<="00000000000000000000000000000000";

mem<=&#39;0&#39;;

ok_count_timer<=&#39;1&#39;;

timer_done<=&#39;0&#39;;

elsif(rising_edge(clk)) then

if(counter_clock=150) then 

counter_clock<="00000000000000000000000000000000";

ok_count_timer<=not ok_count_timer; 

else

counter_clock<=counter_clock+1; 

end if;

if(ok_count_timer=&#39;1&#39 then 

if(ms_counter=unsigned(reg1w) ) then 

timer_done<=&#39;1&#39;;

else

ms_counter<=ms_counter+1;

timer_done<=&#39;0&#39;;

end if;

end if;

 

end if; 

 

end process; 

 

end a;

 

i use system clock (50 Mhz) and i try to divide it , after i increment accumulator 

of my timer and when is equal than register preset i set timer_done .

timer_done i copy in first bit of status register .

But after all i cannot understand how to have a clock every 100ms (for example)

Here i post Nios II .C file 

 

#include "count_binary.h"

 

sDato count;

sDato mem;

sDato val;

#define out val.B.B7

#define puls count.B.B5

#define fc count.B.B6

 

// REGISTER

#define CONTROL_REGISTER 0

#define STATUS_REGISTER 0

#define PRESET 1

#define ACTUAL_TIME_REGISTER 2

 

 

static void count_led()

{

IOWR_ALTERA_AVALON_PIO_DATA(PM_OUT_BASE, count.W);

}

 

//funzione che scrive gli Output 

static void Write_Output()

{

IOWR_ALTERA_AVALON_PIO_DATA(PM_OUT_BASE, val.W);

}

 

//funzione per scrivere gli 8 led pizzamicro 

static void out_led()

{

#ifdef PM_OUT_BASE

IOWR_ALTERA_AVALON_PIO_DATA(PM_OUT_BASE, count.W);

#endif

}

 

 

 

int main(void)

int i;

IOWR(TON_0_BASE,CONTROL_REGISTER,0);

 

while( 1 ) 

{

if(count.B.B7)

{

IOWR(TON_0_BASE,PRESET,12000000);

IOWR(TON_0_BASE,CONTROL_REGISTER,1);

}

else

{

IOWR(TON_0_BASE,PRESET,0);

IOWR(TON_0_BASE,CONTROL_REGISTER,0);

}

count.W=IORD_ALTERA_AVALON_PIO_DATA(PM_IN_BASE) ; 

 

if((count.B.B0) & (!mem.B.B0))

{

val.W++;

mem.B.B0=1;

if(val.W>255){val.W=0;}

}

if(!count.B.B0)

{

mem.B.B0=0;

}

 

 

 

// val.B.B7=(count.B.B5 | val.B.B7) & !count.B.B6;

out=(puls | out) & ! fc;

 

i=IORD(TON_0_BASE,STATUS_REGISTER);

val.B.B6=i & 0x01;

 

Write_Output();

 

 

}

 

return(0);

}

 

 

I would like to know how to generate a 100ms clock to use in my timer 

for incrementing accumulator register 

thanks to eveybody 

walter

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