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Altera_Forum
Honored Contributor I
977 Views

Creating Ethernet Frames

I've got an Aria V starter board with Marvell PHY. I'm trying to get some data from the board to the PC over the ethernet. The QSYS system is all wired up and I can do DMAs from an internal memory to the TSE core. And I can see the TX light blink on the PHY. So it seems like the HW is all there.  

 

The frames to be sent are being assembled in C code using Nios2. The question is do I need to add the preamble to the frame myself or is this a MAC operation?  

 

Also, are there any tricks regarding the byte ordering using the scatter gather DMA->TSE?
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8 Replies
Altera_Forum
Honored Contributor I
50 Views

 

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The question is do I need to add the preamble to the frame myself or is this a MAC operation?  

 

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You only need to add the Ethernet frame data payload. The MAC takes care of preamble and all the ethernet media and physical layer dependent stuff. 

Anyway, it's up to you adding MAC address fields (source and destination) and if I remember correctly, you also need to shift the frame in the packet data array by a 2 byte offset. 

I'd suggest using Wireshark or any other packet sniffing software in order to find out what the board is really transmitting. Maybe those tx led blinks are malformed packets which can't be correctly received by PC. 

Please note that, all this assumes you hw is ok, I mean you don't have any problem with fpga configuration, timing and so on. 

 

Regards
Altera_Forum
Honored Contributor I
50 Views

Ah thank you, I am using wire shark and not getting good frames on the PC. But I didn't realize the 2 byte offset was necessary. Does anyone know where this is documented? I actually figured out the 2 byte offset by trial and error but would like to read about that offset from some Altera literature if it exists.

Altera_Forum
Honored Contributor I
50 Views

I don't know where, and if, any documentation is available on this point. 

Basically I did the same as you: trial and error. I started peeking into library source code called by a standard ethernet project, for example SSS template; then I eventually found that the lower level code loaded ethernet packet data with the offset defined by ETHHDR_BIAS. 

If I remember correctly you can find some information in the Forum; try searching for ETHHDR_BIAS.
Altera_Forum
Honored Contributor I
50 Views

It is described on page 3-3 of the tse user guide (http://www.altera.com/literature/ug/ug_ethernet.pdf), option "Align packet headers to 32-bit  

boundaries (applicable to 32-bit FIFO only)". 

This 2-byte padding enabled to align the 14-byte Ethernet packet to 32-bit boundaries so that the rest of the packet is aligned. The Interniche driver uses this to prevent from having to shift every word after the Ethernet header. This option can be turned off it you don't need it (but as said in the documentation in this case it won't work with the Interniche driver any more).
Altera_Forum
Honored Contributor I
50 Views

thanks guys, I ended up finding the setting in the TSE guide like you posted. Makes sense. I am looking at my ethernet frames on a logic analyzer and all looks well but still not packets making it to wireshark. I am not doing any kind of initialization on the Marvel chip other than a reset. It appears to auto negotiate and come up with the correct speed setting and TX light blinks when I throw a frame at it.  

 

Is there any required initialization for the Marvel PHY or should it just work out of reset?  

 

thanks!
Altera_Forum
Honored Contributor I
50 Views

I got it working!  

 

The TX clock needed to be adjusted with reference to the TX data to get the 1us setup time.
Altera_Forum
Honored Contributor I
50 Views

1ns you mean?

Altera_Forum
Honored Contributor I
50 Views

 

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1ns you mean? 

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yes just needed clock to data relationship adjusted. I wish the TSE included a programmable clock phase shift adjuster. :)
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