Custom Avalon MM-Master component that share On-chip memory with CPU

[Altera_Forum]

Hello all, 

I have a simple custom Avalon MM-Master component  -- Avalon Master Sample Memory Writer library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity avalon_mem_writer is port ( avm_clk : in std_logic; avm_reset : in std_logic; avm_address : out std_logic_vector(31 downto 0); avm_write : out std_logic; avm_writedata : out std_logic_vector(7 downto 0); avm_waitrequest : in std_logic ); end entity; architecture rtl of avalon_mem_writer is type state_type is (idle_state, write_state); signal state : state_type; signal avm_address_index : unsigned(31 downto 0); begin process (avm_clk, avm_reset) begin if avm_reset = '1' then state <= idle_state; avm_address_index <= x"00000000"; elsif (rising_edge(avm_clk)) then case state is when idle_state => if(avm_waitrequest='0') then state <= write_state; end if; when write_state => avm_address_index <= avm_address_index + 1; if(avm_address_index = x"0000000FF") then avm_address_index <= x"00000000"; end if; if(avm_waitrequest='1') then state <= idle_state; end if; end case; end if; end process; avm_address <= x"00000000"; -- std_logic_vector(avm_address_index); avm_writedata <= std_logic_vector(avm_address_index(7 downto 0)); process (state) begin case state is when idle_state => avm_write <= '0'; when write_state => avm_write <= '1'; when others => null; end case; end process; end rtl;   that simply write continuosly to onchip-memory.  I want to share On-chip memory used by my component with NIOS CPU but if I connect both onchip memory isn't written. Should I connect another component (maybe an arbiter) between memory and masters or is automatically inserted?  Thnak you

[Altera_Forum]

--- Quote Start ---    I want to share On-chip memory used by my component with NIOS CPU but if I connect both onchip memory isn't written. Should I connect another component (maybe an arbiter) between memory and masters or is automatically inserted?   --- Quote End ---    The arbitration logic is created automatically by Qsys.   Your problem is likely that your handling of 'waitrequest' is incorrect, but you could probably dodge the issue by making the onchip RAM dual port and connecting the NIOS to one port, and your logic to the other.  When 'waitrequest' is asserted, you need to freeze your outputs. Only when 'write=1' and 'waitrequest=0' can you consider the write transaction to have been accepted by the slave.  If you're just getting started and will be doing this for a while, I would suggest spending the time to get a good testbench using the Avalon Verification IP up and running and it will help save you time in the long run.

[Altera_Forum]

I have written testbench and this is result (only difference with code is that address is incremented) 

 http://www.alteraforum.com/forum/attachment.php?attachmentid=10026&stc=1   When waitrequest is HIGH on the next rising edge "write" signal is LOW, is wrong?  I will check Avalon Verification IP  Thanks and sorry for my english why? EDIT: With Dual Port onchip-memory works like a charm! But without it does not work..

[Altera_Forum]

In the "write_state", when 'waitrequest=1' you transition to "idle_state" where 'write' is de-asserted. 

 If this happens in your system, the write that you thought you had performed will never have been executed.

[Altera_Forum]

In the example testbench posted I want to write 0 at address 0, 1 at address 1, etc.. 

"waitrequest" is asserted on falling edge of clock at 0.3ns, at the next rising clock state go to idle and so 2 is not written but when state go again to "write_state" 2 is written correctly at address 2 or I am wrong?

[Altera_Forum]

In the waveform you posted, the write to address 2 would be accepted at the 5.5ns mark.

[Altera_Forum]

Yes but I can't accept it before, wait request is on falling edge

[Altera_Forum]

--- Quote Start ---  Yes but I can't accept it before, wait request is on falling edge  --- Quote End ---    I don't understand your question or if you are still having difficulty with this?

[Altera_Forum]

I can't accept it is referred to signal. I used dual port and all is fine.

[Altera_Forum]

I have some questions for you both. I am working hard to make my custom instruction read from the on_chip_memory_2. My custom instruction is configured as MM Master. It sometimes read correctly, but sometimes don't.  

 1) Which transfer mode On_chip_memory_2 by default uses? Fixed Latency? Should I wait for waitrequest os for readdatavalid? Looking at On_chip_memory_2 block diagram on Qsys, I realized that it doesn't have either read, waitrequest or readdatavalid signals.  2) If I try your recommendations to use on_chip_memory_2 second port, how should I access it? With an Avalon MM as well or wiring my component direct to its ports?  Thanks,  Gustavo

[Altera_Forum]

Onchip-memory by itself has fixed latency. However, if multiple masters sharing the same onchip-memory port, Qsys interconnect will insert waitrequest/readdatavalid signals.  

 If you are sharing the same onchip memory port, you will need at least the waitrequest signal. If waitrequest is high, you need to keep the read signal high. Once it de-asserted, the readdata will be valid. This means that you will need to perform multi-cycle type custom instruction that stalls until the waitrequest goes low. I am guessing that the reads sometimes not working for your case because the onchip-memory misses your read access entirely when waitrequest is asserted.  If you enable dual port on the onchip-memory and connect your custom instruction to the second port, it will have fixed latency access. You can just re-use the Avalon MM connections.  Do refer to:https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/manual/mnl_avalon_spec.pdf, figure 3-3.