Nios® II Embedded Design Suite (EDS)
Support for Embedded Development Tools, Processors (SoCs and Nios® II processor), Embedded Development Suites (EDSs), Boot and Configuration, Operating Systems, C and C++
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
12455 Discussions

Custom accelerator circuit design with DMA

Altera_Forum
Honored Contributor II
900 Views

Good Morning, 

 

I am running a C program on Linux (builded with buildroot) on the HPS (Cyclone V, DE1-SoC Board), now I want to replace a function with a custom FPGA circuit. 

 

This function reads two matrix, then gives a resulting matrix. This custom hcircuit read the two matrix from the SDRAM of the HPS, than rewrite the result on the same SDRAM. 

1- I want to know if I can use a DMA controller to do this or I must transfer the data using the CPU. 

2- If I can use the DMA controller, is there any documentation about it, how to use it with a custom circuit. 

 

Thanks
0 Kudos
2 Replies
Altera_Forum
Honored Contributor II
132 Views

The DMA on the Cyclone V can definitely deal with this. 

I can't comment on how to implement this on Linux, but here's the key information for a "bare-metal" implementation. 

- The DMA is the "ARM PrimeCell" PL330 module from ARM. You can retrieve the technical manual from the ARM web-site. 

- The Cyclone V handbook also has a section that greatly help understand how to use & program the PL330. 

- Your requirements involves triggers and these are listed in the DMA section of the Cyclone V handbook. 

- You can find the base address of the DMA registers in the Appendix section of the Cyclone V handbook. 

- You should be able to use the hwlib in the SocEDS do program the PL330 for your specific needs; if not, then it should be easily modifiable 

 

Regards
Altera_Forum
Honored Contributor II
132 Views

Old topic but in case anyone is interested to obtain an example of transferring the data from FPGA (using DMA soft IP) to the HPS SDRAM, here is the link: 

https://www.altera.com/support/support-resources/design-examples/soc/fpga-to-hps-bridges-design-exam...
Reply