Hi,I'm trying to get started with Quartus, SoPC Builder and VHDL. As a test I want to implement an internal register file CI (or maybe two) to simply write something on register, do some operations (Hello world) and than get my saved written value from the rister. My code for "write" instuction
library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity write_to_reg is port ( ncs_cis0_dataa : in std_logic_vector(31 downto 0) ; -- cis0.dataa ncs_cis0_datab : in std_logic_vector(31 downto 0) ; -- .datab ncs_cis0_result : out std_logic_vector(31 downto 0); -- .result ncs_cis0_c : in std_logic_vector(4 downto 0); -- .c ncs_cis0_writerc : in std_logic -- .writerc ); end entity write_to_reg; architecture rtl of write_to_reg is signal dataa_unsig : unsigned(31 downto 0); signal datab_unsig : unsigned(31 downto 0); signal result_unsig : unsigned(31 downto 0); begin dataa_unsig <= unsigned(ncs_cis0_dataa); datab_unsig <= unsigned(ncs_cis0_datab); p1: process(dataa_unsig, datab_unsig) begin result_unsig <= datab_unsig - dataa_unsig; end process p1; ncs_cis0_result <= std_logic_vector(result_unsig); end architecture rtl;Now I don't know if that's right. I use the C macro to call my CI, its always delivers result as return value. I tryed to set the values of ncs_cis0_a and ncs_cis0_readra in the VHDL port description, got same result. In this forum I fond some description about the C macros don't work for the Internal Register CI (can't post links, it's in alteraforum showthread.php?t=30902). Didn't worked for me too. I don't know what to do anymore, maybe someone can help me. I thought it would be easy.... Thank you.
You need to implement the internal register file yourself.The most that the 'readra' and 'readrb' bits do it stop the instruction pipeline stall that happens when the referenced registers have just been read (I'm not sure they even do that).