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Valued Contributor III
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Cyclone 5 PLLs part II

Part I of my question involved being able to re-configure PLLs from Linux and that part is now working great. 

 

Part II - I'm trying to create a low jitter clock with a frequency range from 1000Hz to 40MHz off of the 50MHz reference clock provided by the board, I'm using an ATLAS / Soc dev board. 

 

Prior to attempting to use the on chip PLL I was using a simple DDS (counter) to perform this task but the jitter was terrible, with a variation of one 50MHz clock cycle as the counter rolled over to odd values in order to provide an average freq. 

 

My test frequency for jitter is 7MHz. I have no jitter at 8MHz, where the counters align at a nice divisor. 

 

Here's my problem / question. The PLL setup has the exact same jitter profile as a stand alone counter. I'm not getting any benefit from utilizing the PLL at all. It looks as though the PLL is just providing a counter / divider structure like the one I already had in place. 

 

I'm using some C++ code to develop the M, N, C values for the PLL config. The values I come up with are working with respect to correct frequency but as I said, jitter is bad. 

 

So... my question is two parts: 

1) Is there a weighting I should place on choosing M, N, C? Should one be chosen first? Should some be larger than others? I'm looking for general rules. 

2) I have not utilized the fractional portion of the PLL - not sure how to configure it? How do I take my calculations and derive a setting for the fractional value? Is it a MOD() function? 

 

Thanks for your help, 

Jon Herr  

 

-- snippet of calculation code: 

 

const int n_max = 65536, c_max = 65536, m_max = 65536; 

 

// FOUT = (FIN * M) / (N * C) 

 

 

for (n = 1; n < n_max; ++n) 

for (c = 1; c < c_max; ++c) 

for (m = 1; m < m_max; ++m) 

//Fref = Fin / n; 

//Fvco = Fin * (m / n); 

dFout = (dFin * m) / (n * c); 

 

if (dFout == dBitRate) 

std::cout << "n = " << n << " c = " << c << " m = " << m << std::endl; 

std::exit(0); 

}
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Valued Contributor III
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--- Quote Start ---  

The PLL setup has the exact same jitter profile as a stand alone counter. 

--- Quote End ---  

 

Don't understand what you are trying to achieve. Are you using the FPGA PLL with a succeeding DDS frequency divider as before? Then you'll get of course the usual DDS jitter of one DDS input clock cycle. 

 

According to the parameters in your code, you are using integer PLL mode. It generates - by nature - an output clock with no systematic jitter, but some phase noise which might be inappropriate for high performance applications. But surely better than DDS. Integer PLL is however limited to M/(N*C) frequency ratios. 

 

Alternatively you could use PLL in fractional mode. Fractional PLL operation is also introducing jitter, but less than DDS.
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Valued Contributor III
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--- Quote Start ---  

Don't understand what you are trying to achieve. Are you using the FPGA PLL with a succeeding DDS frequency divider as before? Then you'll get of course the usual DDS jitter of one DDS input clock cycle. 

 

According to the parameters in your code, you are using integer PLL mode. It generates - by nature - an output clock with no systematic jitter, but some phase noise which might be inappropriate for high performance applications. But surely better than DDS. Integer PLL is however limited to M/(N*C) frequency ratios. 

 

Alternatively you could use PLL in fractional mode. Fractional PLL operation is also introducing jitter, but less than DDS. 

--- Quote End ---  

 

 

I'm trying to achieve 0.01% jitter of the target clock rate, if possible. I've tried integer mode and fractional (not quite clear on how to calculate the fractional part without the spreadsheet). Both integer mode and fractional have the same jitter at 7MHz. I would expect better performance, so I assume I'm doing something wrong. 

 

Is there a benefit to running the PLL internal frequency at a higher rate? Say by setting the M-counter at a higher value, then using other ratios to bring the output rate back down?  

 

That's what I'm asking, is there a bias towards setting the M, N, C, k values for best performance? Some stand alone clock synthesizer ICs have rules about the order in which variables are chosen and why. Stability, jitter, etc.
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Valued Contributor III
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Any ideas? Can anyone point me to detailed information about the PLL vco and filter circuitry? Min, max vco freq and etc? Thanks, Jon

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