Hi all,I'm new in altera world. My first board is cyclone 5 soc development board. I'm interested in pcie applications. From rocket board side, I found an example project but I couldn't compile it. https://rocketboards.org/foswiki/projects/pcierootportwithmsi -- it is source of the project https://rocketboards.org/foswiki/pub/projects/pcierootport/cv_soc_pcie_rp.pdf -- project tutorial First of all, I get some messages because of the ip compatibility and warned me to upgrade. I mark the automatic upgrade to the project but it failed after the process. file:///C:/Users/herdinc/Downloads/Fpga_qsys/fpga_qsys/cv_soc_rp_simplified_design//pcie_rp_ed_5csxfc6.ipregen.rpt -- this is error file of this failure How can I solve the problem and succesfully program my device? Thank you very much in advence, herdinc
The ip compatibility is most likely due to different version of Quartus (used for creating the project) and the one in your PC. If you open Qsys and regenerate the qsys design, then you should see that the warning goes away when you are compiling it in Quartus.
Hi Sunshine,I have tried this attempt but it couldn't regenerate qsys at the project too. It still gives me errors ERROR MESSAGE --------------- Error: alt_xcvr_reconfig_0: couldn't open "filelist.csv": no such file or directory while executing "open "$csvfile" r" invoked from within "set fh [open "$csvfile" r]" (procedure "parse_filelist_from_csv_report" line 2) invoked from within "parse_filelist_from_csv_report $csvfile" invoked from within "set filelist [parse_filelist_from_csv_report $csvfile]" (procedure "::alt_xcvr::utils::ipgen::ipgenerate" line 24) invoked from within "::alt_xcvr::utils::ipgen::ipgenerate $filepath $filename $fileset $arglist" invoked from within "set filelist [::alt_xcvr::utils::ipgen::ipgenerate $filepath $filename $fileset $arglist]" (procedure "xreconf_generate_qsys_soc" line 10) invoked from within "xreconf_generate_qsys_soc QUARTUS_SYNTH" (procedure "fileset_quartus_synth" line 2) invoked from within "fileset_quartus_synth alt_xcvr_reconfig" Error: Generation stopped, 32 or more modules remaining Error: ip-generate failed with exit code 1: 2 Errors, 4 Warnings ---------------- It couldn't generate the qysys by hand too. I couldn't find any suggest related with this . What can be the meaning?
Unfortunately, I am not really sure what could be the root cause of your issue. I have a slightly different setup (Quartus 16.0 lite version, Windows 10) - from the design downloaded the link below:https://releases.rocketboards.org/release/2015.10/pcie-ed/hw/ I manage to open Qsys and run "Generate HDL.." successfully for both the full design and the simple design (no modification was done on either .qsys file). I chose the HDL design files as "Verilog" and Simulation Model as "None". Just to confirm, you did install Quartus in its default directory right?