Can you show me the exact error message that you got?
Also, how do you do programming? Are you programming the FPGA using Quartus Programmer or via NIOS II?
i am programming with both .sof file from quartus programmer and .elf file from nios ii.
while programming from quartus programmer its working fine .but on loading with nios ii .its comming error verify failed betweeen memory locations 0x40000and 0x43270 like that i dont understand the cause of this error.
jtag is detecting .
and also i have another doubt .
while assigning the pin assignments in cyclone iii
part number EP3c80ufbga484i7
error shows while compiling like can't fit the design in fitter and placing.
can't place multiple pins assigned to pin location D1,k1,e2.
i checked all the other pins i didnt place these any where in pin planner .
its showing pin d1 assigned to ALTERA_ASDO_DATA
pin e2 to ALTERA_FLASH_nCE_nCSO.
but we didnt route these pins to those assigned pins.
i want to know if these pins are reserved or something else
please find a solution for this also